DETAILED ACTION
The office action is in response to the application filed received on December 20, 2023.
The Oath was received on December 20, 2023.
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 20, 2023 has been considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 15-20 are rejected under U.S.C. 103 as being unpatentable over James Aweya et. al. (USPub No.: US 20170288801 A1, hereinafter “Aweya”) in a view of Tariq Haddad et. al. (USPub No.: US 10404447 B1, hereinafter “Haddad”).
Regarding claim 1, Aweya teaches that an apparatus, comprising: a memory configured to store: and a processor communicatively coupled to the memory and configured to: (Aweya, in Paragraphs [0041] and [0204]-[0205], that a slave device is connected to a master device having a master clock over a network, wherein the slave device includes a slave clock and a processor arranged to exchange with the master device, timing messages and record timestamps. The system is implemented in a computer system that includes the hardware, software and data storage devices.) a plurality of clock source selection operations configured to enable selection of one or more clock sources; (Aweya, in Fig. 2 and in Paragraphs [0019], teaches that the GrandMaster provides the time reference for one or more slave devices. These slave devices can act as master devices for further hierarchical layers of slave devices. PTP provides a mechanism (i.e., Best Master Clock Algorithm) for slave clocks to select the best master clock in their respective synchronization domain. The selection is performed according to the PTP attributes of the GrandMaster (e.g. PTP priority, clock class).) and a plurality of clock analysis operations configured to perform a shallow analysis of the one or more clock sources or an in-depth analysis of the one or more clock sources; (Aweya, in Paragraphs [0015]-[0016] and [0019], teaches that in the claim, two clock analysis operations are indicated: a shallow analysis and a in-depth analysis. The shallow method is a concise method as described in Paragraph [0019]. For this method, PTP (Precision Time Protocol) provide a mechanism such as BMCA (Best Master Clock Algorithm) for slave clocks to select the best master clock in their respective synchronization domain based PTP priority or clock class. While, the in-depth method to select further accurate master clock by dealing with the packet delay variation (PDV) and communication path asymmetries (asymmetry in forward and reverse path delays) in the network.) receive a first clock and a second clock from a first network device; (Aweya, in Fig. 2 and in Paragraphs [0020]-[0021], teaches for the two-step clocks, the slave device receives from a master device or a boundary clocks (the first network device) a Sync message (the first clock message) and the Follow_Up message (the second clock message) that contains the exact time of its transmission as shown in Fig. 2.)
Aweya does not explicitly teach that determine that the first clock and the second clock are not currently able to lock; measure a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determine a first clock error based on the first time drift and the first duration of the first time drift; compare the first clock error to a first threshold value representative of a first error tolerance; determine whether the first clock error is greater than the first threshold value; in response to determining that the first clock error is equal to or less than the first threshold value, identify a second threshold value representative of a second error tolerance; and generate a first report indicating that the first clock is stable.
Haddad teaches that determine that the first clock and the second clock are not currently able to lock; (Haddad, in Fig. 1 and 3 and in Col. 6, Lines 23-32, teaches that in Fig. 1 and 3 FIG. 3 shows the operation of state machine controller 22 to place PLL block 24 into idle state 34 (unlocking state). The state machine controller 22 places the PLL block 24 in the idle state 34 if it was previously in the monitoring state 26 and the stream 12 (a clock stream) becomes active, meaning incoming packets move from a state where they do not carry valid frequency and timing information to a state where the TSU 14 (timestamp unit) determines that they carry valid frequency and timing information, or in response to initialization/soft reset from block 38. Thus, by this way, the first clock (the first clock stream) and the second clock (the second clock stream) are determined as an Idle state that indicates the streams are not currently able to lock.) measure a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determine a first clock error based on the first time drift and the first duration of the first time drift; compare the first clock error to a first threshold value representative of a first error tolerance; determine whether the first clock error is greater than the first threshold value; (Haddad, in Fig. 1 and in Col. 4 Lines 4- 41, teaches that In Fig. 1, the real OFM (Offset From Master) block 16 computes the offset from master 15 (OFM phase) (considered as the first clock error based on the first time drift) using both SyncEventingress TimeStamp and DelReq TimeStamp timestamps as shown in the equation of Col. 4, Lines 17-18, where syncEventlngressTimestamp is the timestamp applied to the arriving packets and meanPathDelay is obtained from the DelReq TimeStamps returned by the master. The output phase of the real OFM block 16 (OFM phase) is fed to a StepTime( ) block 18. Time/phase information is stored in the NCO 36 (Numerically Controlled Oscillator), which time/phase information determines the current output of the NCO 36 or shifts the output phase of the associated hardware using dedicated phase offset registers. The StepTime( ) block 18 brings the stored time/phase information to within a programmable threshold offset value relative to the output of the OFM block 16 before a PLL block 24 starts locking operation. The output of the real OFM block 16 is also input to a phase jump detector 19, which asserts a StepTimeinProgress flag as TRUE when a detected phase jump in the incoming active PTP stream exceeds a programmable StepTime threshold. In this case, the offset is needed to be corrected. The threshold can be programmable within the tolerance or the limit predefined and compare it with the offset.) in response to determining that the first clock error is equal to or less than the first threshold value, identify a second threshold value representative of a second error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. The background tasks keep a time count of the period spent in time stepping and a value of the input phase. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the second error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second threshold and the second error tolerance are identified or determined.) and generate a first report indicating that the first clock is stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller generate the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the report for the stability.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of determine that the first clock and the second clock are not currently able to lock; measure a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determine a first clock error based on the first time drift and the first duration of the first time drift; compare the first clock error to a first threshold value representative of a first error tolerance; determine whether the first clock error is greater than the first threshold value; in response to determining that the first clock error is equal to or less than the first threshold value, identify a second threshold value representative of a second error tolerance; and generate a first report indicating that the first clock is stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 2, combination of Aweya and Haddad teaches the features defined in the claims 1, -refer to the indicated claim for reference(s).
Aweya further teaches that receive a third clock and a fourth clock from a second network device; (Aweya, in Fig. 2 and in Paragraphs [0020]-[0021], teaches for the two-step clocks, the slave device receives from another boundary clocks (the second network device) a Sync message (the third clock message) and the Follow_Up message (the fourth clock message) that contains the exact time of its transmission as shown in Fig. 2, since in the system, there can be plurality of the boundary clocks.)
Haddad further teaches that determine that the third clock and the fourth clock are not currently able to lock; (Haddad, in Fig. 1 and 3 and in Col. 6, Lines 23-32, teaches that in Fig. 1 and 3 FIG. 3 shows the operation of state machine controller 22 to place PLL block 24 into idle state 34 (unlocking state). The state machine controller 22 places the PLL block 24 in the idle state 34 if it was previously in the monitoring state 26 and the stream 12 (a clock stream) becomes active, meaning incoming packets move from a state where they do not carry valid frequency and timing information to a state where the TSU 14 (timestamp unit) determines that they carry valid frequency and timing information, or in response to initialization/soft reset from block 38. Thus, by this way, the first clock (the first clock stream) and the second clock (the second clock stream) are determined as an Idle state that indicates the streams are not currently able to lock.) measure a second time drift in the third clock, the second time drift being an offset measured between the third clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a third threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the third clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error in the third clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the third threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determine whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the third threshold value, identify a fourth threshold value representative of a fourth error tolerance; and (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the third threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (third clock stream), i.e. into the normal mode of operation. Further, the fourth threshold can be defined based on the different tolerance.) generate a second report indicating that the third clock is stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller generates the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the report for the stability.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of determine that the third clock and the fourth clock are not currently able to lock; measure a second time drift in the third clock, the second time drift being an offset measured between the third clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a third threshold value representative of a third error tolerance; determine whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the third threshold value, identify a fourth threshold value representative of a fourth error tolerance; and generate a second report indicating that the third clock is stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 3, combination of Aweya and Haddad teaches the features defined in the claims 1, -refer to the indicated claim for reference(s).
Haddad further teaches that measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a second threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the first clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error for the first clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determine whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the second threshold value, identify a third threshold value representative of a fourth error tolerance; and (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the third threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (first clock stream), i.e. into the normal mode of operation. Further, the third threshold can be defined based on the different tolerance.) generate a second report indicating that the first clock remains stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller continuously generates the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the second report for the stability for the first clock.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a second threshold value representative of a third error tolerance; determine whether the second clock error is greater than the second threshold value; in response to determining that the second clock error is less than or equal to the second threshold value, identify a third threshold value representative of a fourth error tolerance; and generate a second report indicating that the first clock remains stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 4, combination of Aweya and Haddad teaches the features defined in the claims 1, -refer to the indicated claim for reference(s).
Haddad further teaches that measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a second threshold value representative of a second error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the first clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error for the first clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the second error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determine whether the second clock error is greater than the second threshold value; in response to determining that the second clock error is greater than the second threshold value; and (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the second threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (first clock stream), i.e. into the normal mode of operation. However, if the second clock error is greater than the second threshold, the state machine controller continues to perform the phase past lock rounds.) generate a second report indicating that the first clock is unstable (Haddad, in Fig. 1 and in Col. 7, Lines 30-35, teaches that if the second clock error is greater than the second threshold, the state machine controller does not generate the flag (means the clock is locked) to represents FastLock or ForcedFastLock or generate the not-active flag such as FastLockNotActive flag, since the state machine controller continues to perform the phase past lock rounds. It is corresponding to the second report for the stability that the first clock is unstable.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to the second threshold value representative of the second error tolerance; determine whether the second clock error is greater than the second threshold value; and in response to determining that the second clock error is greater than the second threshold value, generate a second report indicating that the first clock is unstable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 5, combination of Aweya and Haddad teaches the features defined in the claims 1, -refer to the indicated claim for reference(s).
Aweya further teaches that the first clock error is a Precision Time Protocol (PTP) time error associated with the first clock; and the PTP time error is defined as a rate of change of an offset over time (Aweya, in Fig. 2 and in Paragraph [0022], teaches that At the end of this PTP message exchange, the slave 3 possesses all four timestamps {T1 , T2 , T3 , T4 }. These timestamps may be used to compute the offset (PTP time error) of the slave clock 5 with respect to the master clock 4 and the communication delay of messages between the two clocks. The computation of offset normally assumes that the master-to-slave and slave-to-master path delays are equal, i.e. a symmetrical communication path. Clock frequencies change over time, so periodic message exchanges are required. Because these clock variations change slowly, the period between message exchanges is typically on the order of milliseconds to seconds. Based on this observation, the PTP time error is defined a rate of change of an offset over time.)
Regarding claim 6, combination of Aweya and Haddad teaches the features defined in the claims 1, -refer to the indicated claim for reference(s).
Aweya further teaches that wherein the processor is further configured to determine whether the first clock error is greater than the first threshold value during a maintenance window (Aweya, in Fig. 2 and in Paragraph [0022], The computation of offset normally assumes that the master-to-slave and slave-to-master path delays are equal, i.e. a symmetrical communication path. Clock frequencies change over time, so periodic message exchanges are required. Because these clock variations change slowly, the period between message exchanges is typically on the order of milliseconds to seconds. Based on this assumption, the clock error measurement is calculated based on the PTP messages within maintenance window and as described in the above, the calculated first clock error is compared the predefined threshold. If the error is greater than the threshold, the clock error is detected and the compensation procedure as described in the above is performed.)
Regarding claim 8, Aweya teaches that receiving a first clock and a second clock from a first network device; (Aweya, in Fig. 2 and in Paragraphs [0020]-[0021], teaches for the two-step clocks, the slave device receives from a master device or a boundary clocks (the first network device) a Sync message (the first clock message) and the Follow_Up message (the second clock message) that contains the exact time of its transmission as shown in Fig. 2.)
Aweya does not explicitly teach that determining that the first clock and the second clock are not currently able to lock; measuring a first time drift in the first clock; obtaining a first plurality of timestamps associated with a first duration of the first time drift; determining a first clock error based on the first time drift and the first duration of the first time drift; comparing the first clock error to a first threshold value representative of a first error tolerance; determining whether the first clock error is greater than the first threshold value; in response to determining that the first clock error is equal to or less than the first threshold value, identifying a second threshold value representative of a second error tolerance; and generating a first report indicating that the first clock is stable.
Haddad teaches that determining that the first clock and the second clock are not currently able to lock; (Haddad, in Fig. 1 and 3 and in Col. 6, Lines 23-32, teaches that in Fig. 1 and 3 FIG. 3 shows the operation of state machine controller 22 to place PLL block 24 into idle state 34 (unlocking state). The state machine controller 22 places the PLL block 24 in the idle state 34 if it was previously in the monitoring state 26 and the stream 12 (a clock stream) becomes active, meaning incoming packets move from a state where they do not carry valid frequency and timing information to a state where the TSU 14 (timestamp unit) determines that they carry valid frequency and timing information, or in response to initialization/soft reset from block 38. Thus, by this way, the first clock (the first clock stream) and the second clock (the second clock stream) are determined as an Idle state that indicates the streams are not currently able to lock.) measuring a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determining a first clock error based on the first time drift and the first duration of the first time drift; comparing the first clock error to a first threshold value representative of a first error tolerance; determining whether the first clock error is greater than the first threshold value; (Haddad, in Fig. 1 and in Col. 4 Lines 4- 41, teaches that In Fig. 1, the real OFM (Offset From Master) block 16 computes the offset from master 15 (OFM phase) (considered as the first clock error based on the first time drift) using both SyncEventingress TimeStamp and DelReq TimeStamp timestamps as shown in the equation of Col. 4, Lines 17-18, where syncEventlngressTimestamp is the timestamp applied to the arriving packets and meanPathDelay is obtained from the DelReq TimeStamps returned by the master. The output phase of the real OFM block 16 (OFM phase) is fed to a StepTime( ) block 18. Time/phase information is stored in the NCO 36 (Numerically Controlled Oscillator), which time/phase information determines the current output of the NCO 36 or shifts the output phase of the associated hardware using dedicated phase offset registers. The StepTime( ) block 18 brings the stored time/phase information to within a programmable threshold offset value relative to the output of the OFM block 16 before a PLL block 24 starts locking operation. The output of the real OFM block 16 is also input to a phase jump detector 19, which asserts a StepTimeinProgress flag as TRUE when a detected phase jump in the incoming active PTP stream exceeds a programmable StepTime threshold. In this case, the offset is needed to be corrected. The threshold can be programmable within the tolerance or the limit predefined and compare it with the offset.) in response to determining that the first clock error is equal to or less than the first threshold value, identifying a second threshold value representative of a second error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. The background tasks keep a time count of the period spent in time stepping and a value of the input phase. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the second error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second threshold and the second error tolerance are identified or determined.) and generating a first report indicating that the first clock is stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller generate the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the report for the stability.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of determine that the first clock and the second clock are not currently able to lock; measure a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determine a first clock error based on the first time drift and the first duration of the first time drift; compare the first clock error to a first threshold value representative of a first error tolerance; determine whether the first clock error is greater than the first threshold value; in response to determining that the first clock error is equal to or less than the first threshold value, identifying a second threshold value representative of a second error tolerance; and generating a first report indicating that the first clock is stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 9, combination of Aweya and Haddad teaches the features defined in the claims 8, -refer to the indicated claim for reference(s).
Aweya further teaches that receiving a third clock and a fourth clock from a second network device; (Aweya, in Fig. 2 and in Paragraphs [0020]-[0021], teaches for the two-step clocks, the slave device receives from another boundary clocks (the second network device) a Sync message (the third clock message) and the Follow_Up message (the fourth clock message) that contains the exact time of its transmission as shown in Fig. 2, since in the system, there can be plurality of the boundary clocks.)
Haddad further teaches that determining that the third clock and the fourth clock are not currently able to lock; (Haddad, in Fig. 1 and 3 and in Col. 6, Lines 23-32, teaches that in Fig. 1 and 3 FIG. 3 shows the operation of state machine controller 22 to place PLL block 24 into idle state 34 (unlocking state). The state machine controller 22 places the PLL block 24 in the idle state 34 if it was previously in the monitoring state 26 and the stream 12 (a clock stream) becomes active, meaning incoming packets move from a state where they do not carry valid frequency and timing information to a state where the TSU 14 (timestamp unit) determines that they carry valid frequency and timing information, or in response to initialization/soft reset from block 38. Thus, by this way, the first clock (the first clock stream) and the second clock (the second clock stream) are determined as an Idle state that indicates the streams are not currently able to lock.) measuring a second time drift in the third clock, the second time drift being an offset measured between the third clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtaining a second plurality of timestamps associated with a second duration of the second time drift; determining a second clock error based on the second time drift and the second duration of the second time drift; comparing the second clock error to a third threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the third clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error in the third clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the third threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determining whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the third threshold value, identifying a fourth threshold value representative of a fourth error tolerance; and (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the third threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (third clock stream), i.e. into the normal mode of operation. Further, the fourth threshold can be defined based on the different tolerance.) generating a second report indicating that the third clock is stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller generates the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the report for the stability.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of determining that the third clock and the fourth clock are not currently able to lock; measuring a second time drift in the third clock, the second time drift being an offset measured between the third clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtaining a second plurality of timestamps associated with a second duration of the second time drift; determining a second clock error based on the second time drift and the second duration of the second time drift; comparing the second clock error to a third threshold value representative of a third error tolerance; determining whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the third threshold value, identifying a fourth threshold value representative of a fourth error tolerance; and generating a second report indicating that the third clock is stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 10, combination of Aweya and Haddad teaches the features defined in the claims 8, -refer to the indicated claim for reference(s).
Haddad further teaches that measuring a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtaining a second plurality of timestamps associated with a second duration of the second time drift; determining a second clock error based on the second time drift and the second duration of the second time drift; comparing the second clock error to a second threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the first clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error for the first clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determining whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the second threshold value, identifying a third threshold value representative of a fourth error tolerance; and (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the third threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (first clock stream), i.e. into the normal mode of operation. Further, the third threshold can be defined based on the different tolerance.) generating a second report indicating that the first clock remains stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller continuously generates the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the second report for the stability for the first clock.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of measuring a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtaining a second plurality of timestamps associated with a second duration of the second time drift; determining a second clock error based on the second time drift and the second duration of the second time drift; comparing the second clock error to a second threshold value representative of a third error tolerance; determining whether the second clock error is greater than the second threshold value; in response to determining that the second clock error is less than or equal to the second threshold value, identifying a third threshold value representative of a fourth error tolerance; and generating a second report indicating that the first clock remains stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 11, combination of Aweya and Haddad teaches the features defined in the claims 8, -refer to the indicated claim for reference(s).
Haddad further teaches that measuring a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtaining a second plurality of timestamps associated with a second duration of the second time drift; determining a second clock error based on the second time drift and the second duration of the second time drift; comparing the second clock error to a second threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the first clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error for the first clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determining whether the second clock error is greater than the second threshold value; and in response to determining that the second clock error is greater than the second threshold value, (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the second threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (first clock stream), i.e. into the normal mode of operation. However, if the second clock error is greater than the second threshold, the state machine controller continues to perform the phase past lock rounds.) generating a second report indicating that the first clock is unstable (Haddad, in Fig. 1 and in Col. 7, Lines 30-35, teaches that if the second clock error is greater than the second threshold, the state machine controller does not generate the flag (means the clock is locked) to represents FastLock or ForcedFastLock or generate the not-active flag such as FastLockNotActive flag, since the state machine controller continues to perform the phase past lock rounds. It is corresponding to the second report for the stability that the first clock is unstable.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to the second threshold value representative of the second error tolerance; determine whether the second clock error is greater than the second threshold value; and in response to determining that the second clock error is greater than the second threshold value, generating a second report indicating that the first clock is unstable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 12, combination of Aweya and Haddad teaches the features defined in the claims 8, -refer to the indicated claim for reference(s).
Aweya further teaches that the first clock error is a Precision Time Protocol (PTP) time error associated with the first clock; and the PTP time error is defined as a rate of change of an offset over time (Aweya, in Fig. 2 and in Paragraph [0022], teaches that At the end of this PTP message exchange, the slave 3 possesses all four timestamps {T1, T2, T3, T4}. These timestamps may be used to compute the offset (PTP time error) of the slave clock 5 with respect to the master clock 4 and the communication delay of messages between the two clocks. The computation of offset normally assumes that the master-to-slave and slave-to-master path delays are equal, i.e. a symmetrical communication path. Clock frequencies change over time, so periodic message exchanges are required. Because these clock variations change slowly, the period between message exchanges is typically on the order of milliseconds to seconds. Based on this observation, the PTP time error is defined a rate of change of an offset over time.)
Regarding claim 13, combination of Aweya and Haddad teaches the features defined in the claims 8, -refer to the indicated claim for reference(s).
Aweya further teaches that determining whether the first clock error is greater than the first threshold value during a maintenance window (Aweya, in Fig. 2 and in Paragraph [0022], The computation of offset normally assumes that the master-to-slave and slave-to-master path delays are equal, i.e. a symmetrical communication path. Clock frequencies change over time, so periodic message exchanges are required. Because these clock variations change slowly, the period between message exchanges is typically on the order of milliseconds to seconds. Based on this assumption, the clock error measurement is calculated based on the PTP messages within maintenance window and as described in the above, the calculated first clock error is compared the predefined threshold. If the error is greater than the threshold, the clock error is detected and the compensation procedure as described in the above is performed.)
Regarding claim 15, Aweya teaches that a non-transitory computer readable medium storing instructions that when executed by a processor cause the processor to: (Aweya, in Paragraphs [0204]-[0205] and [0206]-[0207], teaches that the systems and methods may be implemented in a computer system that includes the hardware, software and any non-transitory medium or media which can be read and accessed directly by a computer or computer system and can carry programs to perform the method(s).) receive a first clock and a second clock from a first network device; (Aweya, in Fig. 2 and in Paragraphs [0020]-[0021], teaches for the two-step clocks, the slave device receives from a master device or a boundary clocks (the first network device) a Sync message (the first clock message) and the Follow_Up message (the second clock message) that contains the exact time of its transmission as shown in Fig. 2.)
Aweya does not explicitly teach that determine that the first clock and the second clock are not currently able to lock; measure a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determine a first clock error based on the first time drift and the first duration of the first time drift; compare the first clock error to a first threshold value representative of a first error tolerance; determine whether the first clock error is greater than the first threshold value; in response to determining that the first clock error is equal to or less than the first threshold value, identify a second threshold value representative of a second error tolerance; and generate a first report indicating that the first clock is stable.
Haddad teaches that determine that the first clock and the second clock are not currently able to lock; (Haddad, in Fig. 1 and 3 and in Col. 6, Lines 23-32, teaches that in Fig. 1 and 3 FIG. 3 shows the operation of state machine controller 22 to place PLL block 24 into idle state 34 (unlocking state). The state machine controller 22 places the PLL block 24 in the idle state 34 if it was previously in the monitoring state 26 and the stream 12 (a clock stream) becomes active, meaning incoming packets move from a state where they do not carry valid frequency and timing information to a state where the TSU 14 (timestamp unit) determines that they carry valid frequency and timing information, or in response to initialization/soft reset from block 38. Thus, by this way, the first clock (the first clock stream) and the second clock (the second clock stream) are determined as an Idle state that indicates the streams are not currently able to lock.) measure a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determine a first clock error based on the first time drift and the first duration of the first time drift; compare the first clock error to a first threshold value representative of a first error tolerance; determine whether the first clock error is greater than the first threshold value; (Haddad, in Fig. 1 and in Col. 4 Lines 4- 41, teaches that In Fig. 1, the real OFM (Offset From Master) block 16 computes the offset from master 15 (OFM phase) (considered as the first clock error based on the first time drift) using both SyncEventingress TimeStamp and DelReq TimeStamp timestamps as shown in the equation of Col. 4, Lines 17-18, where syncEventlngressTimestamp is the timestamp applied to the arriving packets and meanPathDelay is obtained from the DelReq TimeStamps returned by the master. The output phase of the real OFM block 16 (OFM phase) is fed to a StepTime( ) block 18. Time/phase information is stored in the NCO 36 (Numerically Controlled Oscillator), which time/phase information determines the current output of the NCO 36 or shifts the output phase of the associated hardware using dedicated phase offset registers. The StepTime( ) block 18 brings the stored time/phase information to within a programmable threshold offset value relative to the output of the OFM block 16 before a PLL block 24 starts locking operation. The output of the real OFM block 16 is also input to a phase jump detector 19, which asserts a StepTimeinProgress flag as TRUE when a detected phase jump in the incoming active PTP stream exceeds a programmable StepTime threshold. In this case, the offset is needed to be corrected. The threshold can be programmable within the tolerance or the limit predefined and compare it with the offset.) in response to determining that the first clock error is equal to or less than the first threshold value, identify a second threshold value representative of a second error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. The background tasks keep a time count of the period spent in time stepping and a value of the input phase. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the second error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second threshold and the second error tolerance are identified or determined.) and generate a first report indicating that the first clock is stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller generate the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the report for the stability.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of determine that the first clock and the second clock are not currently able to lock; measure a first time drift in the first clock; obtain a first plurality of timestamps associated with a first duration of the first time drift; determine a first clock error based on the first time drift and the first duration of the first time drift; compare the first clock error to a first threshold value representative of a first error tolerance; determine whether the first clock error is greater than the first threshold value; in response to determining that the first clock error is equal to or less than the first threshold value, identify a second threshold value representative of a second error tolerance; and generate a first report indicating that the first clock is stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 16, combination of Aweya and Haddad teaches the features defined in the claims 15, -refer to the indicated claim for reference(s).
Aweya further teaches that receive a third clock and a fourth clock from a second network device; (Aweya, in Fig. 2 and in Paragraphs [0020]-[0021], teaches for the two-step clocks, the slave device receives from another boundary clocks (the second network device) a Sync message (the third clock message) and the Follow_Up message (the fourth clock message) that contains the exact time of its transmission as shown in Fig. 2, since in the system, there can be plurality of the boundary clocks.)
Haddad further teaches that determine that the third clock and the fourth clock are not currently able to lock; (Haddad, in Fig. 1 and 3 and in Col. 6, Lines 23-32, teaches that in Fig. 1 and 3 FIG. 3 shows the operation of state machine controller 22 to place PLL block 24 into idle state 34 (unlocking state). The state machine controller 22 places the PLL block 24 in the idle state 34 if it was previously in the monitoring state 26 and the stream 12 (a clock stream) becomes active, meaning incoming packets move from a state where they do not carry valid frequency and timing information to a state where the TSU 14 (timestamp unit) determines that they carry valid frequency and timing information, or in response to initialization/soft reset from block 38. Thus, by this way, the first clock (the first clock stream) and the second clock (the second clock stream) are determined as an Idle state that indicates the streams are not currently able to lock.) measure a second time drift in the third clock, the second time drift being an offset measured between the third clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a third threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the third clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error in the third clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the third threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determine whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the third threshold value, identify a fourth threshold value representative of a fourth error tolerance; and (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the third threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (third clock stream), i.e. into the normal mode of operation. Further, the fourth threshold can be defined based on the different tolerance.) generate a second report indicating that the third clock is stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller generates the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the report for the stability.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of determine that the third clock and the fourth clock are not currently able to lock; measure a second time drift in the third clock, the second time drift being an offset measured between the third clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a third threshold value representative of a third error tolerance; determine whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the third threshold value, identify a fourth threshold value representative of a fourth error tolerance; and generate a second report indicating that the third clock is stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 17, combination of Aweya and Haddad teaches the features defined in the claims 15, -refer to the indicated claim for reference(s).
Haddad further teaches that measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a second threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the first clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error for the first clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determine whether the second clock error is greater than the third threshold value; in response to determining that the second clock error is less than or equal to the second threshold value, identify a third threshold value representative of a fourth error tolerance; and (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the third threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (first clock stream), i.e. into the normal mode of operation. Further, the third threshold can be defined based on the different tolerance.) generate a second report indicating that the first clock remains stable (Haddad, in Fig. 1, teaches that after correction of the clock errors, the state machine controller continuously generates the flag (means the clock is locked) to represents FastLock or ForcedFastLock. It is corresponding to the second report for the stability for the first clock.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a second threshold value representative of a third error tolerance; determine whether the second clock error is greater than the second threshold value; in response to determining that the second clock error is less than or equal to the second threshold value, identify a third threshold value representative of a fourth error tolerance; and generate a second report indicating that the first clock remains stable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 18, combination of Aweya and Haddad teaches the features defined in the claims 15, -refer to the indicated claim for reference(s).
Haddad further teaches that measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to a second threshold value representative of a third error tolerance; (Haddad, in Col. 4, Lines 4-41 and in Col. 6, Lines 45-58, teaches as described in Col. 4, Lines 36-39, the output of the OFM block (OFM phase/time offset: the first clock error in the first clock stream) as the input of the jump detector is compared by the jump detector with the programmable threshold. If the offset is less than or equal to the threshold, the StepTimeProgress flag is set as False, while, if the offset is larger than the threshold, the flag is set as TRUE. When the flag is true, the state machine controller to activate the StepTime block 18 and to palace the PLL block in the Steptime State. As described in Col. 5, Lines 52-Col. 6, Lines, 1-6, during this state a background estimate of the current frequency is performed by taking the derivative of the phase to enable the PLL 24 to be properly initialized before moving back into normal PLL operation (or Fastlock). While stepping the time in a time of day register in the NCO, a background function keeps track of any changes to the frequency offset. Upon exit from the StepTime state 32, the final value of DF is loaded into the Integration Memory, Imem 94. Upon exiting StepTime state, the second time/phase difference (offset, the second clock error for the first clock stream: It is considered as the second time drift or offset between third clock and PTP DPLL, since this is the input of DPLL (the type II PLL).) is calculated and using this, the final frequency offset (DF) is calculated. This residual error is cleared to below a programmable threshold (defined in ns (NanoSecond): the second threshold or the third error tolerance) by performing prespecified number of phase fast lock rounds in ForcedFastLockState, as described in Col. 8, Lines 27-37. In this process, the second time drift (offset) is determined as the DPLL input and it is compared with the programmable threshold.) determine whether the second clock error is greater than the second threshold value; and in response to determining that the second clock error is greater than the second threshold value, (Haddad, in Col. 8, Lines 27-37, teaches that by comparing the second time/phase offset with the programmable threshold, the phase fast lock rounds are performed until the error is cleared. If the error is less than or equal to the second threshold (since the threshold is programmable, the threshold can be varying based on the configuration.), the FastLockinProgress flag is cleared and the state machine controller 22 switches the PLL block 24 into the Type-II PLL (DPLL) state 28, in the presence of an active stream (first clock stream), i.e. into the normal mode of operation. However, if the second clock error is greater than the second threshold, the state machine controller continues to perform the phase past lock rounds.) generate a second report indicating that the first clock is unstable (Haddad, in Fig. 1 and in Col. 7, Lines 30-35, teaches that if the second clock error is greater than the second threshold, the state machine controller does not generate the flag (means the clock is locked) to represents FastLock or ForcedFastLock or generate the not-active flag such as FastLockNotActive flag, since the state machine controller continues to perform the phase past lock rounds. It is corresponding to the second report for the stability that the first clock is unstable.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya and Haddad to include the technique of measure a second time drift in the first clock, the second time drift being an offset measured between the first clock and an on-chip Precision Time Protocol (PTP) Digital Phase-Locked Loop (DPLL); obtain a second plurality of timestamps associated with a second duration of the second time drift; determine a second clock error based on the second time drift and the second duration of the second time drift; compare the second clock error to the second threshold value representative of the second error tolerance; determine whether the second clock error is greater than the second threshold value; and in response to determining that the second clock error is greater than the second threshold value, generate a second report indicating that the first clock is unstable of Haddad in the system of Aweya to provide a controller implementing a state machine that provides a seamless transition between the different system conditions while maintaining the required clock limits, to perform ultra-fast locking with a large time offset between master and server nodes serviced by clock recovery devices. (Haddad, see Col. 2, Lines 27-30 and Lines 38-41).).
Regarding claim 19, combination of Aweya and Haddad teaches the features defined in the claims 15, -refer to the indicated claim for reference(s).
Aweya further teaches that the first clock error is a Precision Time Protocol (PTP) time error associated with the first clock; and the PTP time error is defined as a rate of change of an offset over time (Aweya, in Fig. 2 and in Paragraph [0022], teaches that At the end of this PTP message exchange, the slave 3 possesses all four timestamps {T1, T2, T3, T4}. These timestamps may be used to compute the offset (PTP time error) of the slave clock 5 with respect to the master clock 4 and the communication delay of messages between the two clocks. The computation of offset normally assumes that the master-to-slave and slave-to-master path delays are equal, i.e. a symmetrical communication path. Clock frequencies change over time, so periodic message exchanges are required. Because these clock variations change slowly, the period between message exchanges is typically on the order of milliseconds to seconds. Based on this observation, the PTP time error is defined a rate of change of an offset over time.)
Regarding claim 20, combination of Aweya and Haddad teaches the features defined in the claims 15, -refer to the indicated claim for reference(s).
Aweya further teaches that determining whether the first clock error is greater than the first threshold value during a maintenance window (Aweya, in Fig. 2 and in Paragraph [0022], The computation of offset normally assumes that the master-to-slave and slave-to-master path delays are equal, i.e. a symmetrical communication path. Clock frequencies change over time, so periodic message exchanges are required. Because these clock variations change slowly, the period between message exchanges is typically on the order of milliseconds to seconds. Based on this assumption, the clock error measurement is calculated based on the PTP messages within maintenance window and as described in the above, the calculated first clock error is compared the predefined threshold. If the error is greater than the threshold, the clock error is detected and the compensation procedure as described in the above is performed.)
Claims 7 and 14 are rejected under U.S.C. 103 as being unpatentable over James Aweya et. al. (USPub No.: US 20170288801 A1, hereinafter “Aweya”) in a view of Tariq Haddad et. al. (USPub No.: US 10404447 B1, hereinafter “Haddad”) and in a view of Daniel Rivaud et. al. (USPub No.: US 20170214516 A1, hereinafter “Rivaud”)
Regarding claim 7, combination of Aweya and Haddad teaches the features defined in the claims 1, -refer to the indicated claim for reference(s).
Combination of Aweya and Haddad does not explicitly teach that wherein the processor is further configured to determine whether the first clock error is greater than the first threshold value outside of a maintenance window.
Rivaud teaches that wherein the processor is further configured to determine whether the first clock error is greater than the first threshold value outside of a maintenance window (Rivaud, in Fig. 3-5 and in Paragraph [0012], teaches that Holdover may describe a period of time when a computing system becomes disconnected from a reference clock source, e.g., by a natural disaster. The reference clock source may be a clock source located on a master clock or any clock reference source with higher priority (e.g., a clock source with better accuracy) than a local oscillator device. During holdover, a phase locked loop (PLL) device may obtain an extracted clock signal using an oscillator signal from the local oscillator device instead of a reference clock signal from the reference clock source. Based on this observation, the first clock error is calculated based on the oscillator-based reference clock signal, instead of the clock source on the master device and this error is compared and detected with the determined threshold adjusted based on the oscillator-based reference signal.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya, Haddad, and Rivaud to include the technique of wherein the processor is further configured to determine whether the first clock error is greater than the first threshold value outside of a maintenance window of Rivaud in the system of combination of Aweya and Haddad to provide a method for managing holdover, when the system is disconnected from a reference clock source, to obtain an extracted clock signal from a phase locked loop (PLL) device, to determine, using the oscillator signal and the extracted clock signal, an amount of oscillator drift for the local oscillator device, and to determine, using the amount of oscillator drift, an amount of holdover time for the PLL device. (Rivaud, see Paragraphs [0004] and [0012]).).
Regarding claim 14, combination of Aweya and Haddad teaches the features defined in the claims 8, -refer to the indicated claim for reference(s).
Rivaud teaches that determining whether the first clock error is greater than the first threshold value outside of a maintenance window (Rivaud, in Fig. 3-5 and in Paragraph [0012], teaches that Holdover may describe a period of time when a computing system becomes disconnected from a reference clock source, e.g., by a natural disaster. The reference clock source may be a clock source located on a master clock or any clock reference source with higher priority (e.g., a clock source with better accuracy) than a local oscillator device. During holdover, a phase locked loop (PLL) device may obtain an extracted clock signal using an oscillator signal from the local oscillator device instead of a reference clock signal from the reference clock source. Based on this observation, the first clock error is calculated based on the oscillator based reference clock signal, instead of the clock source on the master device and this error is compared and detected with the determined threshold adjusted based on the oscillator based reference signal.
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Aweya, Haddad, and Rivaud to include the technique of determining whether the first clock error is greater than the first threshold value outside of a maintenance window of Rivaud in the system of combination of Aweya and Haddad to provide a method for managing holdover, when the system is disconnected from a reference clock source, to obtain an extracted clock signal from a phase locked loop (PLL) device, to determine, using the oscillator signal and the extracted clock signal, an amount of oscillator drift for the local oscillator device, and to determine, using the amount of oscillator drift, an amount of holdover time for the PLL device. (Rivaud, see Paragraphs [0004] and [0012]).).
Conclusion
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/JAEYOUNG KWAK/Examiner, Art Unit 2472
/KEVIN T BATES/Supervisory Patent Examiner, Art Unit 2472
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