Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 6-8, 14, 15, 17, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210074914 A1) hereafter referred to as Lee in view of Kanamori et al. (US 20170287928 A1) hereafter referred to as Kanamori
In regard to claim 1 Lee teaches [see Fig. 2A “the data storage structure 46 may form a single-level memory cell”] a vertical type memory device, comprising:
a word line mold [“stack structure 18”] on at least a portion of a substrate [“the lower structure 3 may include a lower base 5”];
a first pillar structure [“vertical structure 33 may be formed in the hole 30 to penetrate the stack structure 18 and the lower buffer layer 17”] in a channel hole within the word line mold;
wherein the first pillar structure includes a first gate insulating layer [“gate dielectric layer 36”] and a cell channel layer [“channel semiconductor layer 38”] on an inner wall of the channel hole, a variable resistance layer [“In an example embodiment, the data storage structure 46 includes a variable resistive material that has a non-uniform concentration of vacancies along its width”] on one side of the cell channel layer, an upper surface of the variable resistance layer being at a height lower [see top of Fig. 2A] than a height of an upper surface of the cell channel layer in the channel hole, a first filling insulating layer [“the core region 55 may be configured as an insulating pillar formed of an insulating material, e.g., a silicon oxide, or the like”] in the channel hole, and a connection pad [“pad pattern 57”] in an upper portion of the first filling insulating layer inside the channel hole, and
but does not teach:
a string select line mold on the word line mold and the first pillar structure; and
a second pillar structure in a string select line hole inside the string select line mold, the string select line hole overlapping at least a portion of the channel hole in a vertical direction perpendicular to an upper surface of the substrate,
wherein the second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer within the string select line hole and connected to the connection pad, and a second filling insulating layer at least partially filling the string select line hole on the select channel layer.
See Lee teaches “conductive line 79 may be configured as a bit line”.
See Kanamori teaches string selection for bit lines, see Fig. 9
a string select line mold [“Each of the first and second string select lines SSL1 and SSL2 may include a first conductive pattern 192 and a second conductive pattern 194”] on the word line mold [i.e. the “stack structure ST”] and the first pillar structure; and
a second pillar structure [“Referring to FIGS. 8A, 8B and 9, each of the first and second string channel pillars SCP1 and SCP2 may include the string vertical channel section 222, the string vertical insulation layer 224, the string conductive pattern 226, and a gap-fill pattern 228”] in a string select line hole inside the string select line mold, the string select line hole overlapping [“the pad D may be in contact with the string vertical channel section 222 penetrating the first interlayer dielectric layer 172 and one of the first and second string select structures SLS1 and SLS2”] at least a portion of the channel hole in a vertical direction perpendicular to an upper surface of the substrate,
wherein the second pillar structure includes a second gate insulating layer [“string vertical insulation layer 224 may be disposed between the string vertical channel section 222 and one of the first and second string select lines SSL1 and SSL2, and extend in the vertical direction along the outer wall of the string vertical channel section 222”] on an inner wall of the string select line hole, a select channel layer [“string vertical channel section 222”] on one side of the second gate insulating layer within the string select line hole and connected to [“the pad D may be in contact with the string vertical channel section 222”] the connection pad, and a second filling insulating layer [“gap-fill pattern 228 may be disposed in an inner space surrounded by the vertical channel section 222. The gap-fill pattern 228 may include an insulating material (e.g., a silicon oxide layer, a silicon nitride layer, etc.)”] at least partially filling the string select line hole on the select channel layer.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Lee to include a string select line mold on the word line mold and the first pillar structure; and a second pillar structure in a string select line hole inside the string select line mold, the string select line hole overlapping at least a portion of the channel hole in a vertical direction perpendicular to an upper surface of the substrate, wherein the second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer within the string select line hole and connected to the connection pad, and a second filling insulating layer at least partially filling the string select line hole on the select channel layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to be able to select the string to electrically operate a specific memory string, and to save space by placing the select transistor on the memory pillar.
In regard to claim 2 Lee and Kanamori as combined teaches [see Lee Fig. 2A “stack structure 18 may include interlayer insulating layers 21 and gate layers 24 alternately layered”] wherein the word line mold includes a first stack structure including a plurality of cell insulating layers and a first electrode layer between the plurality of cell insulating layers.
In regard to claim 3 Lee and Kanamori as combined teaches [see Lee Fig. 2A ] wherein the plurality of cell insulating layers comprises at least an uppermost [“uppermost interlayer insulating layer 21U”] cell insulating layer and a lower cell insulating layer [“interlayer insulating layers 21”] that is between the uppermost cell insulating layer and the substrate,
but does not state and a cross-sectional thickness of the uppermost cell insulating layer is greater than a cross-sectional thickness of the lower cell insulating layer.
See Lee Fig. 2A see that the uppermost interlayer insulating layer 21U has to accomodate the pad thickness and additional vertical spacing between the bottom of the pad and the uppermost gate layer, whereas the other layers interlayer insulating layers 21 are only vertical spacing between the transistors.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “and a cross-sectional thickness of the uppermost cell insulating layer is greater than a cross-sectional thickness of the lower cell insulating layer”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 4 Lee and Kanamori as combined teaches [see Lee Fig. 2A] wherein sidewalls of the connection pad contact the cell channel layer within the channel hole.
In regard to claim 5 Lee and Kanamori as combined teaches wherein the string select line mold includes a second stack structure including a plurality of string select insulating layers [see that plurality is more than 1, see combination, see Kanamori Fig. 9 see “a first insulation pattern 210, a first string select line SSL1, and a second insulation pattern 212 that are sequentially stacked on the first interlayer dielectric layer 172”] and a second electrode layer [“Each of the first and second string select lines SSL1 and SSL2 may include a first conductive pattern 192 and a second conductive pattern 194”] between the plurality of string select insulating layers.
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210074914 A1) hereafter referred to as Lee in view of Kanamori et al. (US 20170287928 A1) hereafter referred to as Kanamori
In regard to claim 9 Lee teaches [see Fig. 2A “the data storage structure 46 may form a single-level memory cell”] a vertical type memory device, comprising:
a word line mold [“stack structure 18”] on at least a portion of a substrate [“the lower structure 3 may include a lower base 5”];
a first pillar structure [“vertical structure 33 may be formed in the hole 30 to penetrate the stack structure 18 and the lower buffer layer 17”] in a channel hole within the word line mold;
wherein the first pillar structure includes a first gate insulating layer [“gate dielectric layer 36”] and a cell channel layer [“channel semiconductor layer 38”] on an inner wall of the channel hole, a variable resistance layer [“In an example embodiment, the data storage structure 46 includes a variable resistive material that has a non-uniform concentration of vacancies along its width”] that is lower than [see top of Fig. 2A] the cell channel layer, a first filling insulating layer [“the core region 55 may be configured as an insulating pillar formed of an insulating material, e.g., a silicon oxide, or the like”] in the channel hole, a recess hole [see top of Fig. 2A] in the channel hole, and a connection pad [“pad pattern 57”] in the recess hole, a lower surface of the connection pad being lower [see top of Fig. 2A] than an upper surface of the first gate insulating layer, and
but does not teach:
a string select line mold on the word line mold and the first pillar structure; and
a second pillar structure in a string select line hole within the string select line mold, the second pillar structure overlapping the first pillar structure,
the second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer within the string select line hole and connected to the connection pad, and a second filling insulating layer in the string select line hole on the select channel layer.
See Lee teaches “conductive line 79 may be configured as a bit line”.
See Kanamori teaches string selection for bit lines, see Fig. 9
a string select line mold [“Each of the first and second string select lines SSL1 and SSL2 may include a first conductive pattern 192 and a second conductive pattern 194”] on the word line mold [i.e. the “stack structure ST”] and the first pillar structure; and
a second pillar structure [“Referring to FIGS. 8A, 8B and 9, each of the first and second string channel pillars SCP1 and SCP2 may include the string vertical channel section 222, the string vertical insulation layer 224, the string conductive pattern 226, and a gap-fill pattern 228”] in a string select line hole within the string select line mold, the second pillar structure overlapping [“the pad D may be in contact with the string vertical channel section 222 penetrating the first interlayer dielectric layer 172 and one of the first and second string select structures SLS1 and SLS2”] the first pillar structure,
the second pillar structure includes a second gate insulating layer [“string vertical insulation layer 224 may be disposed between the string vertical channel section 222 and one of the first and second string select lines SSL1 and SSL2, and extend in the vertical direction along the outer wall of the string vertical channel section 222”] on an inner wall of the string select line hole, a select channel layer [“string vertical channel section 222”] on one side of the second gate insulating layer within the string select line hole and connected to [“the pad D may be in contact with the string vertical channel section 222”] the connection pad, and a second filling insulating layer [“gap-fill pattern 228 may be disposed in an inner space surrounded by the vertical channel section 222. The gap-fill pattern 228 may include an insulating material (e.g., a silicon oxide layer, a silicon nitride layer, etc.)”] in the string select line hole on the select channel layer.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Lee to include a string select line mold on the word line mold and the first pillar structure; and a second pillar structure in a string select line hole within the string select line mold, the second pillar structure overlapping the first pillar structure, the second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer within the string select line hole and connected to the connection pad, and a second filling insulating layer in the string select line hole on the select channel layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to be able to select the string to electrically operate a specific memory string, and to save space by placing the select transistor on the memory pillar.
In regard to claim 10 Lee and Kanamori as combined teaches wherein the word line mold includes a first stack structure including a plurality of cell insulating layers [see Lee Fig. 2A “stack structure 18 may include interlayer insulating layers 21 and gate layers 24 alternately layered”] and a first electrode layer between the plurality of cell insulating layers.
In regard to claim 11 Lee and Kanamori as combined teaches an uppermost cell insulating layer [“uppermost interlayer insulating layer 21U”] and a lower cell insulating layer [“interlayer insulating layers 21”] but does not state wherein a cross-sectional thickness of the uppermost cell insulating layer, among the plurality of cell insulating layers, is greater than a cross-sectional thickness of the lower cell insulating layer.
See Lee Fig. 2A see that the uppermost interlayer insulating layer 21U has to accomodate the pad thickness and additional vertical spacing between the bottom of the pad and the uppermost gate layer, whereas the other layers interlayer insulating layers 21 are only vertical spacing between the transistors.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein a cross-sectional thickness of the uppermost cell insulating layer, among the plurality of cell insulating layers, is greater than a cross-sectional thickness of the lower cell insulating layer”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 12 Lee and Kanamori as combined teaches wherein the string select line mold includes a second stack structure including a plurality of string select insulating layers [see that plurality is more than 1, see combination, see Kanamori Fig. 9 see “a first insulation pattern 210, a first string select line SSL1, and a second insulation pattern 212 that are sequentially stacked on the first interlayer dielectric layer 172”] and a second electrode layer [“Each of the first and second string select lines SSL1 and SSL2 may include a first conductive pattern 192 and a second conductive pattern 194”] between the plurality of string select insulating layers.
In regard to claim 13 Lee and Kanamori as combined teaches wherein sidewalls of the connection pad contact [see Lee Fig. 2A] the cell channel layer within the channel hole.
Claim(s) 16, 18, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210074914 A1) hereafter referred to as Lee in view of Kanamori et al. (US 20170287928 A1) hereafter referred to as Kanamori
In regard to claim 16 Lee teaches [see Fig. 2A “the data storage structure 46 may form a single-level memory cell”] a vertical type memory device, comprising:
a word line mold [“stack structure 18”] on a substrate [“the lower structure 3 may include a lower base 5”];
a first pillar structure [“vertical structure 33 may be formed in the hole 30 to penetrate the stack structure 18 and the lower buffer layer 17”] in a channel hole within the word line mold;
wherein the first pillar structure includes a first gate insulating layer [“gate dielectric layer 36”] and a cell channel layer [“channel semiconductor layer 38”] on an inner wall of the channel hole, a variable resistance layer [“In an example embodiment, the data storage structure 46 includes a variable resistive material that has a non-uniform concentration of vacancies along its width”] on one side of the cell channel layer at a height lower [see top of Fig. 2A] than a height of the cell channel layer in the channel hole, a first filling insulating layer [“the core region 55 may be configured as an insulating pillar formed of an insulating material, e.g., a silicon oxide, or the like”] in the channel hole, a recess hole [see top of Fig. 2A] in the channel hole, the recess hole being lower [see top of Fig. 2A] than an upper surface of the first gate insulating layer and the cell channel layer, and a connection pad [“pad pattern 57”] on an inner wall of the recess hole and an upper portion [see top of Fig. 2A] of the recess hole, and
but does not teach:
a string select line mold on the word line mold and the first pillar structure; and
a second pillar structure in a string select line hole within the string select line mold, the second pillar structure at least partially overlapping the first pillar structure in a vertical direction perpendicular to an upper surface of the substrate,
wherein the second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer within the string select line hole and connected to the connection pad, and a second filling insulating layer in the string select line hole on the select channel layer.
See Lee teaches “conductive line 79 may be configured as a bit line”.
See Kanamori teaches string selection for bit lines, see Fig. 9
a string select line mold [“Each of the first and second string select lines SSL1 and SSL2 may include a first conductive pattern 192 and a second conductive pattern 194”] on the word line mold [i.e. the “stack structure ST”] and the first pillar structure; and
a second pillar structure [“Referring to FIGS. 8A, 8B and 9, each of the first and second string channel pillars SCP1 and SCP2 may include the string vertical channel section 222, the string vertical insulation layer 224, the string conductive pattern 226, and a gap-fill pattern 228”] in a string select line hole within the string select line mold, the second pillar structure at least partially overlapping [“the pad D may be in contact with the string vertical channel section 222 penetrating the first interlayer dielectric layer 172 and one of the first and second string select structures SLS1 and SLS2”] the first pillar structure in a vertical direction perpendicular to an upper surface of the substrate,
wherein the second pillar structure includes a second gate insulating layer [“string vertical insulation layer 224 may be disposed between the string vertical channel section 222 and one of the first and second string select lines SSL1 and SSL2, and extend in the vertical direction along the outer wall of the string vertical channel section 222”] on an inner wall of the string select line hole, a select channel layer [“string vertical channel section 222”] on one side of the second gate insulating layer within the string select line hole and connected to [“the pad D may be in contact with the string vertical channel section 222”] the connection pad, and a second filling insulating layer [“gap-fill pattern 228 may be disposed in an inner space surrounded by the vertical channel section 222. The gap-fill pattern 228 may include an insulating material (e.g., a silicon oxide layer, a silicon nitride layer, etc.)”] in the string select line hole on the select channel layer.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Lee to include a string select line mold on the word line mold and the first pillar structure; and a second pillar structure in a string select line hole within the string select line mold, the second pillar structure at least partially overlapping the first pillar structure in a vertical direction perpendicular to an upper surface of the substrate, wherein the second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer within the string select line hole and connected to the connection pad, and a second filling insulating layer in the string select line hole on the select channel layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to be able to select the string to electrically operate a specific memory string, and to save space by placing the select transistor on the memory pillar.
In regard to claim 18 Lee and Kanamori as combined teaches wherein the word line mold includes a first stack structure including a plurality of cell insulating layers [see Lee Fig. 2A “stack structure 18 may include interlayer insulating layers 21 and gate layers 24 alternately layered”] and a first electrode layer between the plurality of cell insulating layers, and the string select line mold includes a second stack structure including a plurality of string select insulating layers [see that plurality is more than 1, see combination, see Kanamori Fig. 9 see “a first insulation pattern 210, a first string select line SSL1, and a second insulation pattern 212 that are sequentially stacked on the first interlayer dielectric layer 172”] and a second electrode layer [“Each of the first and second string select lines SSL1 and SSL2 may include a first conductive pattern 192 and a second conductive pattern 194”] between the plurality of string select insulating layers.
In regard to claim 19 Lee and Kanamori as combined teaches wherein sidewalls of the connection pad contact [see Lee Fig. 2A] the cell channel layer within the channel hole.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893