DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
In re to claims 15-24, method claims 15-24 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9, 10-21 and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luff in view of Hari US 2015/031039.
Regarding Claims 1 and 15-16, Luff teaches (Figures 1-5 and 16-17) a control device (controller in IC 102) for a buck-boost switching voltage regulator (BB converter in Fig. 2) comprising a switching circuit (202a-d), the control device configured to perform a current-control (with the controller) of the switching circuit, the switching circuit comprising a first half-bridge (202a-b) having a first high-side switch and a first low-side switch coupled (202a and 202b) in series, a second half-bridge (202c-d) having a second high-side switch and a second low-side switch (202c and 202d) coupled in series, an inductor (Lout) coupled between intermediate nodes of the first and the second half-bridges (Lx1-Lx2) ,a resistor (R), the control device comprising: a filter (208) configured to be coupled to the common reference potential node (circle) and provide a filtered signal; and a loop control circuit (206, 210 and 220) configured to generate
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Luff does not teach a first half-bridge having a first high-side switch and a first low-side switch coupled in series between an input node and a common reference potential node, a second half-bridge having a second high-side switch and a second low-side switch coupled in series between an output node and the common reference potential node, an inductor coupled between intermediate nodes of the first and the second half-bridges, and a shunt resistor coupled between the common reference potential node and a ground, the control device comprising: a filter configured to be coupled to the common reference potential node and provide a filtered signal starting from a shunt voltage measurement across the shunt resistor indicative of a current flowing through the shunt resistor.
Hari teaches (Figures 1, 3 and 6) a first half-bridge (101) having a first high-side switch and a first low-side switch coupled (hd1 and ld1) in series between an input node and a common reference potential node (Vin and 105), a second half-bridge (102) having a second high-side switch and a second low-side switch (hd2 and ld2) coupled in series between an output node (Vout) and the common reference potential node (105), and a shunt resistor (Rcs) coupled between the common reference potential node and a ground (105 and ground), a filter (R3-R4 and C1) configured to be coupled to the common reference potential node (105) and provide a filtered signal (sent to S1) starting from a shunt voltage measurement across the shunt resistor (Rcs) indicative of a current flowing through the shunt resistor (par. 23-24 and 32). (For Example: Par. 17-24 and 31-35)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Luff to include a first half-bridge having a first high-side switch and a first low-side switch coupled in series between an input node and a common reference potential node, a second half-bridge having a second high-side switch and a second low-side switch coupled in series between an output node and the common reference potential node, an inductor coupled between intermediate nodes of the first and the second half-bridges, and a shunt resistor coupled between the common reference potential node and a ground, the control device comprising: a filter configured to be coupled to the common reference potential node and provide a filtered signal starting from a shunt voltage measurement across the shunt resistor indicative of a current flowing through the shunt resistor, as taught by Hari to avoid an excessively long pulse width at the transition, causing unwanted output voltage ripple.
Regarding Claims 2 and 17, Luff teaches (Figures 1-5 and 16-17) wherein the filter (at 208) has a time constant that is variable as a function of the filter control signal (because it changes with the operation of the switches 1602 which are controlled by the same control signal as the 202 switches and the resistor and capacitor are variable, see par. 76-80). (For Example: Par. 35-42, 74, 76-82, 94 and 96)
Regarding Claims 3 and 21, Luff teaches (Figures 1-5 and 16-17) wherein the filter is a low-pass filter (par. 76).
Regarding Claims 6 and 19, Luff teaches (Figures 1-5 and 16-17) wherein the filter (at 208) comprises at least one resistive element having the resistance (Fig. 16 with Rr). (For Example: Par. 35-42, 74, 76-82, 94 and 96)
Regarding Claim 7, Luff teaches (Figures 1-5 and 16-17) wherein the resistive element of the filter comprises a parallel circuit including a filter resistor and a filter switch (Rr with Tri), and wherein the filter switch is controlled by the filter control signal (par. 78). (For Example: Par. 35-42, 74, 76-82, 94 and 96)
Regarding Claim 8, Luff teaches (Figures 1-5 and 16-17) wherein the filter control signal is a first filter control signal (for switch 1602-a), wherein the filter is further configured to receive a second filter control signal (for switch 1602-c) indicative of the actual operating mode of the buck-boost switching voltage regulator (par. 78) and different from the first filter control signal, wherein the resistive element of the filter comprises a parallel circuit having a first branch and a second branch (1602a-b, buck Rr and Cr & 1602c-d boost Rr and Cr) , each branch comprising a respective filter resistor and a respective filter switch connected to each other in series, and wherein the respective filter switch of the first branch is controlled by the first filter control signal (par. 78), and the respective filter switch of the second branch is controlled by the second filter control signal (par. 78). (For Example: Par. 35-42, 74, 76-82, 94 and 96)
Regarding Claims 9 and 20, Luff teaches (Figures 1-5 and 16-17) wherein the filter (at 208) comprises at least one capacitive element having the capacitance.
Regarding Claims 10 and 23, Luff teaches (Figures 1-5 and 16-17) a device.
Luff does not teach further configured to perform a peak-type current-control when the buck-boost switching voltage regulator is in a boost operating mode, and to perform a valley-type current-control when the buck-boost switching voltage regulator is in a buck operating mode.
Hari (Figure 3) further configured to perform a peak-type current-control when the buck-boost switching voltage regulator is in a boost operating mode (boost mode, par. 28), and to perform a valley-type current-control when the buck-boost switching voltage regulator is in a buck operating mode (buck mode, par. 28).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Luff to include further configured to perform a peak-type current-control when the buck-boost switching voltage regulator is in a boost operating mode, and to perform a valley-type current-control when the buck-boost switching voltage regulator is in a buck operating mode, as taught by Hari to avoid an excessively long pulse width at the transition, causing unwanted output voltage ripple.
Regarding Claims 11 and 24, Luff teaches (Figures 1-5 and 16-17) wherein the loop control circuit (206, 210 and 220) comprises: a feedback circuit configured to generate a feedback control signal as a function of a difference between an output voltage and a reference voltage (Fig. 3, with 310 Vfb and Vref); a pulse width modulation (PWM) modulator (with 210) configured to receive the filtered signal (from 208) and the feedback control signal and, in response, generate a modulated signal (sent to 206); and a driving logic circuit (with 206) configured to provide the switching control signals as a function of the modulated signal. (For Example: Par. 35-47)
Regarding Claim 12, Luff teaches (Figures 1-5 and 16-17) a buck-boost switching voltage regulator (Fig. 2) comprising: a control device (controller at IC 102) configured to perform a current-control of a switching circuit (BB converter and resistor in 208), the control device comprising: a filter (at 208) configured to be coupled the switching circuit (see the above drawing of claim 1) and to provide a filtered signal (208 output) from a resistor (R, see the above drawing); and a loop control circuit (206, 210 and 220) configured to generate first high-side, first low- side, second high-side, and second low-side switching control signals (A-D signals), as a function of the filtered signal (with 210 circuitry providing control signal to 206); wherein the filter is further configured to receive a filter control signal (sent to 208 to control switches 1602 and iTri) indicative of an actual operating mode of the buck-boost switching voltage regulator (with 1602, par. 78), wherein the filter control signal (sent to 208 to control the switches) is at least one of the switching control signals (par. 78), and wherein the filter comprises a resistance or capacitance (Rr or Cr) that is variable as a function of the filter control signal (with the control of switches 1602, iTri and the variable resistor and capacitor Rr and Cr); and the switching circuit (BB converter and resistor in 208), comprising: a first half-bridge (202a-b) comprising a first high side switch and a first low side switch coupled in series; a second half-bridge (202c-d) comprising a second high side switch and a second low side switch coupled in series; an inductor (L) coupled between intermediate nodes (Lx1-Lx2) of the first and the second half-bridges (see fig. 16), wherein the first high-side, first low-side, second high-side, and second low-side switches (202) are controlled respectively by the first high-side, first low-side, second high-side, and second low-side switching control signals (from 206) generated by the loop control circuit (206, 210 and 220). (For Example: Par. 35-42, 74, 76-82, 94 and 96)
Luff does not teach a first half-bridge having a first high-side switch and a first low-side switch coupled in series between an input node and a common reference potential node, a second half-bridge having a second high-side switch and a second low-side switch coupled in series between an output node and the common reference potential node, an inductor coupled between intermediate nodes of the first and the second half-bridges, and a shunt resistor coupled between the common reference potential node and a ground, the control device comprising: a filter configured to be coupled to the common reference potential node and provide a filtered signal starting from a shunt voltage measurement across the shunt resistor indicative of a current flowing through the shunt resistor.
Hari teaches (Figures 1, 3 and 6) the control device (controller) comprising: a filter (R3-R4 and C1) configured to be coupled to the common reference potential node (105) and provide a filtered signal (sent to S1) starting from a shunt voltage measurement across a shunt resistor (Rcs) indicative of a current flowing through the shunt resistor (par. 23-24 and 32); and a first half-bridge (101) having a first high-side switch and a first low-side switch coupled (hd1 and ld1) in series between an input node and a common reference potential node (Vin and 105), a second half-bridge (102) having a second high-side switch and a second low-side switch (hd2 and ld2) coupled in series between an output node (Vout) and the common reference potential node (105), and a shunt resistor (Rcs) coupled between the common reference potential node and a ground (105 and ground). (For Example: Par. 17-24 and 31-35)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Luff to include a first half-bridge having a first high-side switch and a first low-side switch coupled in series between an input node and a common reference potential node, a second half-bridge having a second high-side switch and a second low-side switch coupled in series between an output node and the common reference potential node, an inductor coupled between intermediate nodes of the first and the second half-bridges, and a shunt resistor coupled between the common reference potential node and a ground, the control device comprising: a filter configured to be coupled to the common reference potential node and provide a filtered signal starting from a shunt voltage measurement across the shunt resistor indicative of a current flowing through the shunt resistor, as taught by Hari to avoid an excessively long pulse width at the transition, causing unwanted output voltage ripple.
Regarding Claim 13, Luff teaches (Figures 1-5 and 16-17) wherein the filter comprises electrical elements integrated in the control device (IC102 see fig. 1-2).
Regarding Claim 14, Luff teaches (Figures 1-5 and 16-17) wherein the filter (at 208) comprises discrete electrical elements (e.g. transistors, resistors and capacitors).
Claim(s) 4 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luff in view of Hari US 2015/031039 and further in view of Toshiyuki US 2019/0027923.
Regarding Claims 4 and 22, Luff teaches (Figures 1-5 and 16-17) wherein the filter (at 208) is configured to have a first time constant when the buck-boost switching voltage regulator is in a buck operating mode (operation in buck mode and the Vrip output from 208), and a second time constant when the buck-boost switching voltage regulator is in a boost operating mode (Operation in boost mode and Vrip output from 208). (For Example: Par. 35-42, 74, 76-82, 94 and 96)
Luff does not teach wherein the second time constant is greater than the first time constant.
Toshiyuki (Figures 2) wherein the second time constant is greater than the first time constant.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Luff to include wherein the second time constant is greater than the first time constant, as taught by Toshiyuki to improve the accuracy of the sensing signal.
Response to Arguments
Applicant's arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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