DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 05/08/2026.
Currently, claims 1-24 are pending in the application. Currently, claims 4 and 13-24 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of Group I (claims 1-12) and Species I (Figs. 2A & 2B) in the reply filed on 05/08/2026 is acknowledged. The traversal is on the ground(s) that Group I/Species I should be merged with Group I/Species II for examination because the search required for both species would not place an undue or serious burden on the Examiner (see pp. 7-8 of Applicant’s Remarks). This argument is not found persuasive because the species would require a different field of search such as employing different search queries due to the differences in shape and positioning of the backside S/D contact (BSDC) between Species I and II. Further, prior art that may be applicable to one species may not be applicable to another species (e.g., prior art that has a BSDC that is electrically coupled to only a bottom surface of a source/drain structure would read on Species I but would not read on Species II). The requirement is still deemed proper and is therefore made FINAL. Claims 4 and 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-selected invention, there being no allowable generic or linking claim. Claims 1-3 and 5-12 are examined in this Office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/31/2025 and 05/08/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-8, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHENG et al. (US Pub. No. 2022/0052206).
Regarding independent claim 1, Cheng teaches a field effect transistor (FET) structure (Fig. 21D), comprising:
a gate structure (Fig. 21D, 240, ¶ [0029]), extending in a first horizontal direction (X in Fig. 21A) and disposed between a first source/drain (S/D) epitaxial (EPI) structure (Fig. 21D, right 260B, ¶ [0037]) and a second S/D EPI structure (Fig. 21D, left 260B) set apart in a second horizontal direction (Y in Figs. 21A & 21D), the gate structure comprising a channel structure (Fig. 21D, 215’,¶ [0043]) and a vertical metal gate structure (Fig. 21D, 360B, ¶ [0044]), the channel structure comprising a plurality of vertically-stacked, horizontal channels structure (Fig. 21D, stacks of 215’ in 240) connecting the first S/D EPI structure to the second S/D EPI structure in the second horizontal direction (Fig. 21D, 215’ directly contacts left and right 260B and at least partially goes through 360B) through the vertical metal gate structure that at least partially surrounds the plurality of channels (Fig. 21D); and
a backside inter-layer dielectric (ILD) layer (Fig. 21D, 376, ¶ [0060]) disposed below the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Fig. 21D,at least a portion of 376 is on a level vertically below Cheng’s source/drain and gate structures),
wherein the first S/D EPI structure comprises a lower portion (Fig. 21D, portion of right 260B on a level vertically below bottom surface of 240 and embedded in 376) that extends vertically below a bottom surface of the vertical metal gate structure and into the backside ILD layer (Fig. 21D), the lower portion comprising sides and a bottom surface (Fig. 21D), and
wherein at least the bottom surface of the lower portion is electrically coupled to a backside contact (Fig. 21D, 378, ¶ [0061]).
Regarding claim 2, Cheng teaches the FET structure of claim 1, Cheng teaches that the backside contact (Fig. 21D, 378, ¶ [0064]) comprises a trench contact (Fig. 21D, bottom half of 378) extending in the second horizontal direction (Y in Figs. 21A & 21D).
Regarding claim 3, Cheng teaches the FET structure of claim 1, and Cheng teaches that the backside contact (Fig. 21D, 378, ¶ [0064]) comprises a power rail (¶ [0054] teaches that backside conductive features/backside power rails can be formed on bottom surfaces of 260B) for providing VDD or VSS (Cheng does teach the claimed structure of an backside contact/backside power rail. When the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. MPEP § 2112.01(I). “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” Id. (quoting In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)). Accordingly, Cheng discloses an backside power rail structure that necessarily possesses the properties of the claimed structure disclosed in Applicant's claim 3.) to the first S/D EPI structure (Fig. 21D, right 260B, ¶ [0037]).
Regarding claim 6, Cheng teaches the FET structure of claim 1, and Cheng teaches a first coupling material (¶ [0064] teaches that a silicide layer can be in-between Cheng’s source/drain structure and Cheng’s metal layer in 378) disposed between at least a portion of the lower portion of the first S/D EPI structure (Fig. 21D, right 260B, ¶ [0037]) and the backside contact.
Regarding claim 7, Cheng teaches the FET structure of claim 6, and Cheng teaches that the first coupling material (¶ [0064] teaches that a silicide layer can be in-between Cheng’s source/drain structure and Cheng’s metal layer in 378) comprises silicide.
Regarding claim 8, Cheng teaches the FET structure of claim 1, and Cheng teaches that the backside contact (Fig. 21D, 378, ¶ [0061]) comprises at least one of a backside S/D contact (BSDC) structure (¶¶ [0061] & [0064] teaches that Cheng’s backside conductive structure is in contact with an epitaxial source/drain and can therefore be considered to be a backside source/drain contact) or a backside metal (BM) layer structure.
Regarding claim 11, Cheng teaches the FET structure of claim 1, and Cheng teaches that the gate structure (Fig. 21D, 240, ¶ [0029]) comprises a gate- all-around (GAA) structure (¶¶ [0030] & [0044] teaches that Cheng’s device has a GAA transistor structure).
Regarding claim 12, Cheng teaches the FET structure of claim 1, and Cheng teaches a frontside inter-layer dielectric (ILD) layer (Fig. 21D, 270, ¶ [0039]) disposed above the vertical metal gate structure Fig. 21D, 360B, ¶ [0044]), the first S/D EPI structure (Fig. 21D, right 260B, ¶ [0037]), and the second S/D EPI structure Fig. 21D, left 260B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being obvious over CHENG et al. (US Pub. No. 2022/0052206).
Regarding claim 5, Cheng teaches the FET structure of claim 1, and Cheng teaches that the backside contact (Fig. 21D, 378, ¶ [0061]) is in direct contact (¶ [0064] teaches that conductive features 378 and 380 are similar in composition and structure. ¶ [0062] teaches that 380 can be one conductive material. Therefore, it would be obvious that 378 can also be one conductive material in direct contact with Cheng’s source/drain structure because 378 and 380 can be similar in composition and structure) with the lower portion of the first S/D EPI structure (Fig. 21D, bottom surface of right 260B is in direct contact with top surface of 378).
Claim 9 is rejected under 35 U.S.C. 103 as being obvious over CHENG et al. (US Pub. No. 2022/0052206) in view of XIE et al. (US Pub. No. 2024/0105768)
Regarding claim 9, Cheng teaches the FET structure of claim 1.
However, Cheng does not explicitly teach a first etch stop material disposed on at least a bottom surface of the lower portion of the second S/D EPI structure.
However, Xie is a pertinent art that teaches a first etch stop (Fig. 16A, 134, ¶ [0099]) material disposed on at least a bottom surface of the lower portion of the second S/D EPI structure (Fig. 16A, S/D epi, ¶ [0100]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng’s device to further include an etch stop layer according to the teaching of Xie (Fig. 16A) in order to improve epitaxial growth uniformity (Xie ¶ [0099]).
Claim 10 is rejected under 35 U.S.C. 103 as being obvious over CHENG et al. (US Pub. No. 2022/0052206) in view of XIE et al. (US Pub. No. 2024/0105768) and further in view of Yang et al. (US Pub. No. 2022/0352179).
Regarding claim 10, Cheng modified by Xie teaches the FET structure of claim 9, and Xie teaches that the first etch stop material (Fig. 16A, 134, ¶ [0099]) comprises at least one of titanium silicide (TiSi), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), aluminum nitride (AIN), an area-selective deposition (ASD) dielectric, or a silicon- germanium (SiGe) epitaxial layer (¶¶ [0096] & [0099] teaches that 134 can be silicon germanium deposited by CVD. It would be obvious that epitaxial SiGe can be formed through a CVD process (for example, see ¶ [0052] of Yang)).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2021/0111115 by Morrow et al discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2022/0359676 by Chu et al discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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