DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed on 27 July 2026 have been fully considered but they are not persuasive. Applicant argues that the amendments reciting specific transistor attributes (material, size, type) and operating conditions (supply voltage, power levels) distinguishing the driver stage from the second stage patentably define over Levesque and Wang. Examiner disagrees, for the following reasons:
Regarding Claim 1, Levesque explicitly teaches that amplifier stages comprise transistors (§0050) and that the operating modes/conditions of the first stage dictate the required impedance matching provided by the tunable inter-stage network (§0045, §0053, §0090). The physical and electrical characteristics of stage 18's transistors inherently form its configuration and output impedance.
Regarding the dependent claims, Wang explicitly provides the structural and mathematical framework (Formula 1) relating transistor sizing, supply voltage, power level, and output impedance (§0022, §0035). Modifying Levesque's driver/output stages with routine RF transistor selections (e.g., smaller driver transistors, lower driver supply voltage, standard GaN/GaAs materials) amounts to combining known prior art elements according to established principles to achieve predictable results (KSR Int'l Co. v. Teleflex Inc.).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Levesque (US 2017/0012588 A1).
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Fig. 2 of Levesque annotated by the examiner for ease of reference.
Regarding claims 1 and 18, Levesque discloses a power amplifier system. See Abstract; §0050–§0052; Fig. 2.
Levesque discloses a first amplifier stage (18) coupled to a power amplifier input (17) and configured to amplify an input RF signal (The power amplifier 31 includes a first amplifier stage 18 coupled with the power amplifier input 17 and a tunable matching network, such as a tunable inter-stage matching network 19, §0052, Fig. 2).
Levesque second amplifier stage (27) configured to receive the signal from the inter-stage matching network and amplify it to produce a PA output (the PA output 29 through the tunable output matching network 28, §0052, Fig. 2);
Per claim 18, Levesque expressly discloses that the PA output is coupled to an antenna or antenna-facing component such as a duplexer (a component coupled with the PA output, including, but not limited to, a duplexer and an antenna, §0053);
Back to claims 1 and 18 again, Levesque tunable inter-stage matching network (19) disposed between the first and second amplifier stages and expressly configured to couple a first impedance (output impedance of the first stage) to a second impedance (input impedance of the second stage), §0052; §0053 ("Including a tunable matching network in this manner helps absorb an imaginary part of the PA's output impedance . . . This results in an impedance mismatch between the PA output and a component coupled with the PA output . . . The impedance mismatch results in higher insertion loss."); Fig. 2. Furthermore, Levesque discloses that the ratio of impedance transformation provided by the tunable matching network is actively controlled (the capacitance of the first variable capacitor array 500 can be used to control, for example, an input impedance of the RF circuit 1500 and/or to control a ratio of impedance transformation provided by the tunable input matching network 2100, §0090).
Levesque inter-stage matching network is configured and tuned based on the operating characteristics of the first amplifier stage so as to minimize impedance mismatch between stages, §0045 ("for a multi-stage power amplifier, an inter-stage matching network can be matched based on the most frequent operating mode of the power amplifier"); §0053 ("The impedance mismatch results in higher insertion loss, which consequently uses more PA power and reduces the system efficiency."); §0064 ("The tunable network matching networks as described herein improve gain flatness and decreases the IL at the band edges of the power amplifier."). The configuration of the first amplifier stage—including the operating mode under which it is operated and the characteristics of its transistors—thus defines the impedance transformation ratio required to minimize mismatch with the second stage.
Levesque discloses that the configuration of the first amplifier stage specifies at least one operating condition. Specifically, Levesque discloses that the amplifier is operated in different operating modes, such as Envelope Tracking (ET) and Average Power Tracking (APT), and that the inter-stage matching network is matched and tuned based on these operating conditions of the amplifier stage, §0044, §0045, §0055.
Furthermore, Levesque discloses that the amplifier stages inherently comprise transistors as amplifying elements, §0050.
Regarding the amended limitations of claims 1, 11 and 18, at least one operating condition (Levesque teaches operating the PA in different modes such as Envelope Tracking (ET) and Average Power Tracking (APT) (§0044, §0055), which constitute operating conditions defined by the first amplifier stage's configuration. Furthermore, Levesque explicitly teaches that the inter-stage matching network is matched/configured based on these operating conditions and characteristics of the amplifier stage (§0045, §0053, §0064)) of the first amplification stage (Levesque shows a first amplifier stage (18) coupled to a tunable inter-stage matching network (19), which is connected to a second amplifier stage (27) in Fig. 2 and in Fig. 6 shows an RF circuit with a tunable input matching network (2100) / tunable matching network (1500) containing variable capacitor arrays (500)) reduce a difference between the output impedance of the first amplification stage and the input impedance of the second amplification stage (to improve matching between the stages) such that an impedance transformation ratio between the output impedance of the first amplification stage and an input impedance of the second amplification stage is within a threshold of one (tuning the variable capacitor arrays to control and adjust the impedance transformation ratio between stages, §0052, §0090).
wherein a first supply voltage and a second supply voltage are independently specified (Figs. 7, 9 and 10 shows a bias voltage generation circuit (64) generating multiple independent bias/supply voltages (VBIAS1, VBIAS2, VBIAS3) that control separate variable capacitor cells (71a/72a/73a, 71b/72b/73b, 71c/72c/73c) within the variable capacitor arrays of the inter-stage matching network) to reduce the difference between the output impedance of the first amplification stage and the input impedance of the second amplification stage (i.e. to improve the interstage matching) such that the impedance transformation ratio is within the threshold of one (Levesque discloses that the bias voltage generation circuit 64 receives the control signal CNTL, and generates a first bias voltage VBIAS1... a second bias voltage VBIAS2 and a third bias voltage VBIAS3... The bias voltage generation circuit 64 can be used to control the voltage levels of the first, second, and third bias voltages VBIAS1–VBIAS3 to control the capacitances of the first to third variable capacitor arrays, §0106 and explain that independently setting these supply/bias voltage levels directly adjusts array capacitances to configure the impedance transformation ratio across the stages (§0090, §0108).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-17, 19-21 are rejected under 35 U.S.C. 103 as unpatentable over Levesque in view of Wang et al. (US 2014/0097698 A1).
Claim 2 depends on claim 1 and further specifies that the at least one attribute of the transistors in the first amplification stage comprises a type, material, and/or size of the transistors, and that the at least one operating condition comprises a supply voltage.
Levesque discloses amplifier stages comprising transistors (§0050) and that the operating mode of the amplifier (an operating condition) determines the required impedance transformation. To the extent Levesque does not explicitly enumerate transistor type, material, and size as the specific attributes.
In a similar field of endeavor Wang teaches that a power amplifier's output impedance and power efficiency are directly determined by transistor sizing and supply voltage (Formula 1, §0022: the relationship η = V²dd / 2RL demonstrates that output impedance RL and supply voltage Vdd jointly define power efficiency). Wang further teaches that high and low power amplifiers have different output impedances (§0022, §0037–§0038), which corresponds directly to different transistor sizes and/or supply voltages.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to recognize that transistor type, material, and size — well-understood determinants of output impedance — are the attributes of the first amplification stage's configuration that define the impedance transformation ratio, as taught by the combined disclosures of Levesque and Wang.
Claim 3 depends on claim 2 and further specifies that the supply voltage is dependent on the transistor material.
Wang teaches at §0022 and Formula 1 that supply voltage (Vdd) and output load impedance (RL) jointly determine power efficiency. Wang further teaches that different power amplifying modules may operate with different supply conditions corresponding to different output power modes. The relationship between transistor material and maximum allowable supply voltage is a fundamental and well-known design consideration in RF amplifier design — for example, GaN transistors support higher supply voltages than silicon CMOS transistors due to their wider bandgap. It would have been obvious to a person of ordinary skill in the art that, when selecting a transistor material for the first amplification stage as taught by the combination of Levesque and Wang, the supply voltage is inherently constrained by and therefore dependent on that material selection, making the limitation of claim 3 obvious.
Claim 4 depends on claim 1 and specifies that the first supply voltage operating the first amplification stage is less than the second supply voltage operating the second amplification stage.
Wang expressly teaches that in a multi-mode power amplifying circuit, the first power amplifier (151) has higher power than the second power amplifier (171) (§0035). Wang's Formula 1 (§0020–§0022) establishes that under a given supply voltage, a higher-power amplifier requires lower output impedance, and conversely, a lower-power amplifier requires higher output impedance. Applied to a cascaded two-stage architecture as disclosed by Levesque, it would have been obvious to a person of ordinary skill in the art to operate the driver (first) stage at a lower supply voltage than the higher-power output (second) stage, since the driver stage handles lower signal levels and a lower supply voltage reduces power dissipation while the output stage requires a higher supply voltage to deliver greater output power. The use of different supply voltages for driver and output stages is a routine and well-known design practice in multi-stage RF power amplifier design.
Claim 5 depends on claim 1 and specifies that the transistors in the first amplification stage are smaller than the transistors in the second amplification stage.
Wang teaches that a higher-power amplifier has a relatively small output impedance and a lower-power amplifier has a relatively large output impedance (§0022, Formula 1). In transistor-level amplifier design, output impedance is inversely related to transistor size — larger transistors present lower output impedance and can deliver higher output power. Accordingly, Wang's teaching that the first (higher-power output) amplifier module has lower output impedance than the second (lower-power) module, combined with Levesque's disclosure of a cascaded first and second amplification stage, renders it obvious that the driver (first) stage transistors would be smaller than the output (second) stage transistors to achieve the desired impedance profile. This is a routine and predictable design choice within the skill of the art.
Claim 6 depends on claim 1 and specifies that the transistor material of the first amplification stage is one of GaN on SiC, GaN on Si, GaAs, SOI, or Si, and that the second amplification stage comprises transistors formed by GaN on SiC or GaN on Si.
Levesque discloses that the amplifier stages include transistors (§0050) and that MOS variable capacitors may be fabricated using silicon-on-insulator (SOI) processes (§0097). Wang teaches that different power amplifying modules have different power levels and output impedances (§0022, §0035), which in practice are implemented using different semiconductor materials. The use of GaN on SiC or GaN on Si for high-power output stages and alternative materials (GaAs, SOI, Si) for lower-power driver stages is a well-established and widely practiced technique in RF power amplifier design, representing a design choice with known and predictable results. It would have been obvious to a person of ordinary skill in the art to select any of these standard semiconductor materials for each respective stage based on the power and impedance requirements as taught by the combination of Levesque and Wang.
Claim 7 depends on claim 1 and specifies that the first and second amplification stages are Doherty amplifiers.
Levesque teaches multi-stage power amplifiers configured for multiple operating modes (§0044–§0055), and Wang discloses parallel power amplifying modules operating in different modes to optimize efficiency (§0024–§0042). The Doherty amplifier architecture — comprising a main amplifier and a peaking amplifier — is a well-known and widely employed technique in RF power amplifier design for improving efficiency at back-off power levels and is the type of amplifier explicitly addressed by the subject claims. It would have been obvious to a person of ordinary skill in the art to implement the amplification stages of Levesque's multi-stage PA as Doherty amplifiers, particularly considering Wang's disclosure of efficiency optimization through selective amplifier operation, as both designs share the fundamental goal of improving power efficiency across a range of output conditions.
Claim 8 depends on claim 1 and specifies that the transistors in the first amplification stage comprise at least one cascode device.
Levesque discloses amplifier stages comprising transistors (§0050) and MOS variable capacitor arrays including cascaded transistor structures (§0086, §0142–§0143). Wang teaches multi-mode amplifier configurations with various transistor arrangements to achieve desired output impedances (§0022). The use of cascode transistor configurations in RF amplifier stages to increase output impedance, improve reverse isolation, and extend the frequency response is a standard and well-known technique in the art. It would have been obvious to a person of ordinary skill to implement the transistors of the first amplification stage as a cascode device to achieve the desired output impedance and impedance transformation ratio as taught by the combination of Levesque and Wang, with a reasonable expectation of success.
Claim 9 depends on claim 1 and specifies that the transistors in the first amplification stage comprise at least one Darlington structure.
As discussed with respect to claim 8, Levesque and Wang together teach multi-stage amplifier configurations with transistor-level design choices made to achieve target impedances and power levels. A Darlington pair configuration is a well-known transistor topology used to increase current gain and modify the effective transistor size and impedance characteristics in amplifier stages. It would have been obvious to a person of ordinary skill in the art to employ a Darlington structure in the first amplification stage as an alternative transistor configuration to achieve the desired impedance transformation ratio taught by the combination of Levesque and Wang, as such configurations are routine design alternatives with predictable performance outcomes.
Claim 10 depends on claim 1 and specifies that the configuration specifies the at least one attribute and operating condition to cause the impedance transformation ratio to be close to the value of one.
Levesque teaches that the inter-stage matching network is tuned to minimize impedance mismatch (§0053) and that the impedance transformation ratio can be controlled via the variable capacitor arrays (§0090). Wang teaches that the second impedance matching circuit matches the output impedance of the second power amplifier to the input impedance of the first impedance matching circuit (§0037), and that the output impedance of the second impedance matching circuit and the input impedance of the first matching circuit are designed to be the same impedance (§0032). This direct impedance matching — i.e., a transformation ratio of one — is precisely what Wang teaches as the operative condition at the inter-stage interface. It would have been obvious to a person of ordinary skill in the art to configure the first amplification stage such that its output impedance closely matches the input impedance of the second stage, yielding an impedance transformation ratio near unity, to minimize insertion loss as taught by the combined disclosures of Levesque and Wang.
Claim 11 is an independent claim directed to a system where the first amplification stage comprises a first main amplifier and first peaking amplifier, and the second amplification stage comprises a second main amplifier and second peaking amplifier, with separate matching networks for the main and peaking signal paths.
Levesque discloses a multi-stage power amplifier with inter-stage matching (§0052, Fig. 2), and Wang discloses a multi-mode amplifying circuit with parallel first and second power amplifying modules each connected to an impedance matching circuit (§0024–§0028, Figs. 1–4). Wang explicitly teaches a parallel architecture in which a first power amplifying module (150) and a second power amplifying module (170) are electrically connected in parallel between the signal input end and the first impedance matching circuit (§0025), with separate matching networks for each path (§0027–§0028). It would have been obvious to a person of ordinary skill in the art to implement the amplification stages of Levesque with a main/peaking Doherty configuration as disclosed in a general sense by Wang's parallel module architecture, and to provide separate matching networks for the main and peaking signal paths as Wang teaches separate matching circuits for parallel amplifier modules, in order to optimize the impedance presented by each sub-amplifier path to the subsequent stage.
Regarding the amended limitations of claim 11, see the related discussion in the rejection of claim 1 above.
Claim 12 depends on claim 11 and recites substantially the same limitations as claim 2 applied to the Doherty/main-peaking configuration of claim 11.
Claim 12 is rejected for the same reasons stated with respect to claim 2, applied to the architecture of claim 11. The combined teachings of Levesque and Wang render it obvious that the configuration of the first amplification stage — including transistor type, material, size, and supply voltage — defines the impedance transformation ratio between the first and second stages of a main/peaking amplifier architecture.
Claim 13 depends on claim 12 and specifies that the supply voltage is dependent on the transistor material, as applied to the Doherty architecture.
Claim 13 is rejected for the same reasons stated with respect to claim 3. The dependence of supply voltage on transistor material is an inherent and well-known physical relationship that applies equally to the main/peaking amplifier architecture of claim 11.
Claim 14 depends on claim 11 and specifies that the first supply voltage operating the first main and peaking amplifiers is less than the second supply voltage operating the second main and peaking amplifiers.
Claim 14 is rejected for the same reasons stated with respect to claim 4. Wang's Formula 1 and the teaching that higher-power amplifiers operate at lower output impedance (§0022) make it obvious to operate the first (driver) Doherty stage at a lower supply voltage than the second (output) Doherty stage.
Claim 15 depends on claim 11 and specifies that transistors in the first amplification stage are smaller than those in the second amplification stage.
Claim 15 is rejected for the same reasons stated with respect to claim 5. Wang's teaching regarding the relationship between transistor sizing, output impedance, and power level (§0022, Formula 1) renders this limitation obvious in the context of the main/peaking amplifier architecture of claim 11.
Claim 16 depends on claim 11 and recites specific transistor materials for the first and second amplification stages.
Claim 16 is rejected for the same reasons stated with respect to claim 6, applied to the main/peaking architecture of claim 11.
Claim 17 depends on claim 11 and specifies that the impedance transformation ratio is close to the value of one, as applied to the Doherty architecture.
Claim 17 is rejected for the same reasons stated with respect to claim 10. Wang teaches that the output impedance of the second matching circuit and the input impedance of the first matching circuit are designed to be the same impedance (§0032), i.e., a transformation ratio approaching unity. It would have been obvious to apply this principle to the main/peaking amplifier architecture of claim 11.
Claim 19 depends on claim 18 and specifies that the operating conditions further include output power from the first amplification stage and gain of the second amplification stage, in addition to supply voltage and transistor attributes.
Levesque discloses that the power amplifier must be designed to support different output power levels and operating modes (§0044), and that matching is optimized based on these operating conditions. Wang expressly teaches that output power is a key parameter in selecting which amplifying module to operate and how to configure the impedance matching (§0022, Formula 1: power efficiency is defined in terms of output load power). Wang further teaches that the second power amplifier has a different (lower) power than the first (§0035), making the gain and output power of each stage explicit design parameters. It would have been obvious to a person of ordinary skill in the art that output power from the first amplification stage and gain of the second amplification stage are operating conditions that, together with supply voltage, characterize the configuration of the amplification stages and define the required impedance transformation ratio, as directly taught by the combined disclosures of Levesque and Wang.
Claim 20 depends on claim 18 and specifies that the first supply voltage is less than the second supply voltage.
Claim 20 is rejected for the same reasons stated with respect to claim 4, applied to the system of claim 18. Wang's Formula 1 and the teaching that high-power amplifiers require lower output impedance (§0022) — which under the same supply voltage corresponds to a different transistor sizing — and the well-known practice of using lower supply voltages for driver stages versus output stages makes it obvious that the first (driver) amplification stage operates at a lower supply voltage than the second (output) amplification stage. There is a clear motivation to combine Levesque's multi-stage PA architecture with Wang's explicit teaching of supply voltage and impedance optimization to achieve this result, with a reasonable expectation of success.
Regarding Claim 21: The Applicant's addition of Claim 21 specifies that the transistor size in the first stage is equal to the transistor size in the second stage. Selecting equal transistor sizes across cascaded stages represents an obvious design choice for a POSITA attempting to simplify process manufacturing and balance inter-stage device characteristics1. Absent a showing of unexpected results arising specifically from equal sizing in combination with the inter-stage matching network, this limitation fails to render the claim patentable over Levesque and Wang.
Conclusion
The prior art Ji et al. (US 20230291359) made of record and not relied upon is considered pertinent to applicant's disclosure. Ji teaches a two stage Doherty amplifier with each stage having a main amplifier and a pealing amplifier as recited in claim 9. Each main amplifier and peaking amplifiers are equipped with adaptive bias circuits. Also, there are interstage matching networks between first main amplifier to the second main amplifier and between first peak amplifier to the second peak amplifier respectively with adjustable impedance ratio using transformers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 It is well-settled that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable range/sizing (e.g., matching transistor dimensions across stages to achieve uniform layout or identical driving capability) is ordinarily within the level of ordinary skill in the art (In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955)).
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