DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-28 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 2, 5, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 20240202416 A1 – hereinafter Hu) in view of Thomson et al. (US 20230088578 A1 – hereinafter Thomson).
Regarding independent claim 1, Hu teaches:
A chip ([0003] – “FIG. 1 is a plan view of an integrated circuit structure” –
an integrated circuit are also referred to as a chip), comprising:
a first cell (110a – Fig. 1 – [0033] – “cell 110a”) comprising:
a first diffusion region (116b – Fig. 1 – [0040] – “diffusion region 116a”) extending in a first direction (x – Fig. 1 – [0022] – “X-axis direction”); and
a first backside contact coupled to a bottom surface of the first diffusion region;
a second cell (115h – Fig. 1 – [0033] – “cell 115h”) comprising:
a second diffusion region (126b – Fig. 1 – [0042] – “diffusion region 126b”) extending in the first direction (x), wherein the second diffusion region (126b) is wider ([0003- - “the short and tall cells” – Fig. 1 shows this) than the first diffusion region (116b) in a second direction (y – Fig. 1 – [0022] – “direction of the Y-axis”) perpendicular to the first direction (x); and
a second backside contact coupled to a bottom surface of the second diffusion region; and
a power rail (410 – Fig. 4 – [0059] – “rail 410 may act as a power rail”) extending under the first cell (110a) and the second cell (115h) in the first
direction (x), wherein the power rail (410) is coupled to the first backside contact and the second backside contact.
Hu does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Thomson teaches
a first backside contact (113a – Fig. 4a – [0056] – “first backside contact 113a”) coupled to a bottom surface of the first diffusion region (103b – Fig. 4a – [0056] – “first diffusion region 103b” – Fig. 4a shows this),
a second backside contact (113b – Fig. 4a – [0056] – “second backside contact 113b”) coupled to a bottom surface of the second diffusion region (107b – Fig. 4a – [0056] – “second diffusion region 107b” – Fig. 4a shows this);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside contact structure as taught by Thomson into Hu.
An ordinary artisan would have been motivated to use the known technique of Thomson in the manner set forth above to produce the predictable result of electrically connecting the chips to the power rails as Thomson states [0027] – “Any number of connection schemes can be used, including frontside-only connections, backside-only connections, and a combination of frontside and backside connections (e.g., frontside contacts to the cathode and backside contacts to the anode).”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 2, Hu as modified by Thomson, teaches claim 1 from which claim 2 depends. Hu does not expressly disclose the limitations of claim 2.
However, in an analogous art, Thomson teaches
further comprising:
a first via (615b – Fig. 6a – [0064] – “backside interconnect 115 includes one or
more dielectric layers 615a, via 615b, and conductor 615c”) disposed between the first backside contact (113a) and the power rail (615c – Fig. 6a – [0064] – “backside interconnect 115 includes one or more dielectric layers 615a, via 615b, and conductor 615c”); and
a second via (615h – Fig. 6c – [0066] – “interconnect 115 includes multiple vias (615b, 615h, and 615i) formed in dielectric 615a, with each via (615b, 615h, and 615i) in contact with a corresponding conductor (615c, 615f, and 615g)”) disposed between the second backside contact (113b) and the power rail (615c – Fig. 6c – [0066] – “interconnect 115 includes multiple vias (615b, 615h, and 615i) formed in dielectric 615a, with each via (615b, 615h, and 615i) in contact with a corresponding conductor (615c, 615f, and 615g)” – this is the power rail).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the backside contact and via structure as taught by Thomson into Hu.
An ordinary artisan would have been motivated to use the known technique of Thomson in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 5, Hu as modified by Thomson, teaches claim 1 from which claim 5 depends. Hu further teaches
wherein:
the first cell (110a) comprises first gates (120a – Fig. 1 – [0041] – “gate
structure 120a”) formed on the first diffusion region (116b), wherein each of the first gates (120a) extends across the first diffusion region (116b) in the second direction (y – Fig. 1 shows this); and
the second cell (115h) comprises second gates (130a – Fig. 1 – [0042] – “gate structures 130a, 130b, 130c”) formed on the second diffusion region (126b), wherein each of the second gates (130a) extends across the second diffusion region (126b) in the second direction (y – Fig. 1 shows this).
Regarding claim 6, Hu as modified by Thomson, teaches claim 5 from which claim 6 depends. Hu further teaches
wherein a height of each of the second gates (130a) in the second
direction (y) is greater than a height of each of the first gates (120a) in the second direction (y – Fig. 1 shows this).
Regarding claim 9, Hu as modified by Thomson, teaches claim 5 from which claim 9 depends. Hu further teaches
wherein the power rail (410) is a ground rail (410 – [0059] – “rail 410 may act as a power rail or a ground rail, e.g., to supply power or ground connection”).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Thomson and Yamaoka et al. (US 7589993 B2 – hereinafter Yamaoka).
Regarding claim 3, Hu as modified by Thomson, teaches claim 1 from which claim 3 depends. Hu and Thomson do not expressly disclose the limitations of claim 3.
However, in an analogous art, Yamaoka teaches
wherein the second diffusion region (Fig. 8 annotated, see below – [10:37-38]
– “diffusion layers 34” – hereinafter ’34-2’) is between 1.1 to 1.4 times wider ([10:63-65] – “the ratio W1/W3 of the gate width W1 of the driver MOS transistors to the gate width W3 of the transfer MOS transistors to be less than 1.4.” – Fig. 8 shows the gate width W1 is the width of the second diffusion region 34) than the first diffusion region (Fig. 8 annotated, see below – [10:37-38] – “diffusion layers 34” – hereinafter ’34-1’) in the second direction (Fig. 8 annotated, see below – hereinafter ’y’).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to the width of the diffusion regions as taught by Yamaoka into Hu and Thomson.
An ordinary artisan would have been motivated to use the known technique of Yamaoka in the manner set forth above to produce the predictable result [2:57-60] – “to ensure a larger static noise margin during read operation. For this reason, the gate width of driver MOS transistor have been manufactured larger than the gate width of the transfer MOS transistor.”
Regarding claim 4, Hu as modified by Thomson, teaches claim 3 from which claim 4 depends. Hu further teaches
wherein the second diffusion region (126b) is offset ([0046] –
“diffusion regions 116, 126” – Fig. 3 shows diffusion region 126 that contains 126b offset in the y direction from diffusion region 116 that contains 116b, therefore 126b is offset from 116b) from the first diffusion region (116b) in the second direction (y).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Thomson and Kinoshita (US 20050156200 A1 – hereinafter Kinoshita).
Regarding claim 3, Hu as modified by Thomson, teaches claim 1 from which claim 3 depends. Hu and Thomson do not expressly disclose the limitations of claim 3.
However, in an analogous art, Kinoshita teaches
wherein a height of the second cell (20a – Fig. 1 – [0029] – “the height of the
second cell 20a to 20c is double that of the first cells 10a to 10k”) in the second
direction ([0008] – “a height covering the entire widths of the p- and n-wells measured along the column direction, the height of the second cell is double that of the first cell” – hereinafter ‘COL’) is approximately two times a height of the first cell (10a – Fig. 1 – [0029] – “the height of the second cell 20a to 20c is double that of the first cells 10a to 10k”) in the second direction (COL – Fig. 1 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the width of the diffusion regions as taught by Kinoshita into Hu and Thomson.
An ordinary artisan would have been motivated to use the known technique of Kinoshita in the manner set forth above to produce the predictable result so as to not limit the size of the transistor being placed in an area between the rails.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Thomson and Mori et al. (US 20210201961 A1 – hereinafter Mori).
Regarding claim 8, Hu as modified by Thomson, teaches claim 1 from which claim 8 depends. Hu and Thomson do not expressly disclose the limitations of claim 8.
However, in an analogous art, Mori teaches
wherein the power rail (518 – Fig. 5 – [0046] – “BPR 518 disposed in the x
direction that provides a third voltage source (e.g., VDD BPR shown in FIG. 2)”) is a supply rail configured to provide a supply voltage (Vdd – [0109]) (mor ([0049] – “BPR 518 provides the VDD BPR power source”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power rail structure as taught by Mori into Hu and Thomson.
An ordinary artisan would have been motivated to use the known technique of Mori in the manner set forth above to produce the predictable result powering a chip.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 10, Hu as modified by Thomson, teaches claim 1 from which claim 10 depends. Hu and Thomson do not expressly disclose the limitations of claim 10.
However, in an analogous art, Mori teaches
wherein the power rail is formed from a backside metal layer (518 – [0046] –
“BPR 518 disposed in the x direction that provides a third voltage source (e.g., VDD BPR shown in FIG. 2)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power rail structure as taught by Mori into Hu and Thomson.
An ordinary artisan would have been motivated to use the known technique of Mori in the manner set forth above to produce the predictable result of producing a backside power rail from the metal used to produce the backside conductive structure. This reduces manufacturing costs and eases the manufacturing method.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Allowable Subject Matter
Claims 11-28 are allowed.
The following is an examiner’s statement of reasons for allowance:
In reference to claim 11, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding a second power rail extending under the first cell and the second cell in the first direction, wherein the second power rail is coupled to a bottom surface of the second diffusion region and a bottom surface of the fourth diffusion region in combination with the other recited limitations.
Claims 12-16 depend on claim 11 and are therefore allowable.
The closest prior art of record is Tzeng et al. (US 20130313615 A1 – hereinafter
Tzeng). Tzeng teaches a power rail (208 – Fig. 1 – [0009] – “conductive traces 208 forming power rails”) extending under the first cell (210 – Fig. 1 – [0010] – “cells 210, 220, 230, 240, 250 and 260”) and the second cell (230 – Fig. 1 – [0010] – “cells 210, 220, 230, 240, 250 and 260”) in the first direction, wherein the first power rail (210) is coupled to a bottom surface of the first diffusion region (216 – Fig. 1 – [0014] – “source and drain regions 216” – this is a diffusion region) and a bottom surface of the third diffusion region (236 – Fig. 1 – [0021] – “source and drain regions 236” – this is a diffusion region). This specific structure of a second power rail with those limitations is not taught or rendered obvious by the prior art of record. The instant application states that the beneficial effect of the opening entirely surrounding the drive circuit is [0002] – “A chip may include many cells (e.g., thousands to millions of cells) laid out on the chip. Each cell may include one or more transistors that are arranged to provide a circuit (e.g., a driver, a logic gate, combinational logic, a latch, or another type of circuit). The layout of each cell may be specified in a standard cell library that defines the layouts for various types of cells that can be placed (i.e., laid out) on the chip.” The layout as claimed allows for different chips of standard sizes to be installed on parallel power bars without modifications to the chip or the power bar layout.
In reference to claim 17, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding a second power rail extending under the first cell and the third cell in the first direction, wherein the second power rail is coupled to a bottom surface of the second diffusion region;
a third power rail extending under the second cell and the third cell in the first direction, wherein the third power rail is coupled to a bottom surface of the third diffusion region and a bottom surface of the sixth diffusion region; and
a fourth power rail extending under the second cell and the third cell in the first direction, wherein the fourth power rail is coupled to a bottom surface of the fourth diffusion region in combination with the other recited limitations.
Claims 18-23 depend on claim 17 and are therefore allowable.
The closest prior art of record is Tzeng et al. (US 20130313615 A1 – hereinafter
Tzeng). Tzeng teaches a power rail (208 – Fig. 1 – [0009] – “conductive traces 208 forming power rails”) extending under the first cell (210 – Fig. 1 – [0010] – “cells 210, 220, 230, 240, 250 and 260”) and the second cell (230 – Fig. 1 – [0010] – “cells 210, 220, 230, 240, 250 and 260”) in the first direction, wherein the first power rail (210) is coupled to a bottom surface of the first diffusion region (216 – Fig. 1 – [0014] – “source and drain regions 216” – this is a diffusion region) and a bottom surface of the third diffusion region (236 – Fig. 1 – [0021] – “source and drain regions 236” – this is a diffusion region). This specific structure of a second power rail with those limitations is not taught or rendered obvious by the prior art of record. The instant application states that the beneficial effect of the opening entirely surrounding the drive circuit is [0002] – “A chip may include many cells (e.g., thousands to millions of cells) laid out on the chip. Each cell may include one or more transistors that are arranged to provide a circuit (e.g., a driver, a logic gate, combinational logic, a latch, or another type of circuit). The layout of each cell may be specified in a standard cell library that defines the layouts for various types of cells that can be placed (i.e., laid out) on the chip.” The layout as claimed allows for different chips of standard sizes to be installed on parallel power bars without modifications to the chip or the power bar layout.
In reference to claim 24, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding a second power rail extending under the second diffusion region in the first direction, wherein the second power rail is coupled to a bottom surface of the second diffusion region and a bottom surface of the fourth diffusion region in combination with the other recited limitations.
Claims 25-28 depend on claim 17 and are therefore allowable.
The closest prior art of record is Tzeng et al. (US 20130313615 A1 – hereinafter
Tzeng). Tzeng teaches a power rail (208 – Fig. 1 – [0009] – “conductive traces 208 forming power rails”) extending under the first cell (210 – Fig. 1 – [0010] – “cells 210, 220, 230, 240, 250 and 260”) and the second cell (230 – Fig. 1 – [0010] – “cells 210, 220, 230, 240, 250 and 260”) in the first direction, wherein the first power rail (210) is coupled to a bottom surface of the first diffusion region (216 – Fig. 1 – [0014] – “source and drain regions 216” – this is a diffusion region) and a bottom surface of the third diffusion region (236 – Fig. 1 – [0021] – “source and drain regions 236” – this is a diffusion region). This specific structure of a second power rail with those limitations is not taught or rendered obvious by the prior art of record. The instant application states that the beneficial effect of the opening entirely surrounding the drive circuit is [0002] – “A chip may include many cells (e.g., thousands to millions of cells) laid out on the chip. Each cell may include one or more transistors that are arranged to provide a circuit (e.g., a driver, a logic gate, combinational logic, a latch, or another type of circuit). The layout of each cell may be specified in a standard cell library that defines the layouts for various types of cells that can be placed (i.e., laid out) on the chip.” The layout as claimed allows for different chips of standard sizes to be installed on parallel power bars without modifications to the chip or the power bar layout.
Any comments considered necessary by applicant must be submitted no later
than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Pertinent Art
For the benefits of the Applicant, US 20200168607 A1, US 8877593 B2, and US 10497693 B1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including a second power rail.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897