DETAILED ACTION
Claims 1-4,6-8 and 10-16 have been examined.
This office action is in response to the communication filed on January 15, 2026.
This office action is made Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Response to Arguments
Applicant's amendments necessitated new ground(s) of rejection under 112(b), 101 abstract idea, and 103 presented in this Office Action.
Applicant argument, see pgs 6-10 of Remarks, with respect to the claims have been fully considered, but were not found persuasive.
With respect to applicant’s argument, “Applicant respectfully submits that the claims are outside of the "mental processes" exception. Rather, the claims are directed to methods and systems for detecting anomalies in a nominal execution of tasks in a processor system and include meaningful claim elements tied to specific hardware configurations rather than generic computer recitations. Furthermore, the claims also include additional elements directed at specific training and utilization of machine learning models for tracking tasks as they are executed, classifying tasks by the machine learning models, and updating classifications based on continued monitoring, all of which are outside of the mental processes exception. Applicant further submits that under Step 2A, Prong two, even if the claims are directed to an abstract idea, the claims successfully integrate an abstract idea into a practical application. Namely, the claims are directed towards the real-time monitoring of a processor system through the detection of possible anomalies that occur during the execution of tasks. The claims recite methods and systems of monitoring the processor system in a manner that promises a low monitoring overhead while simultaneously providing real-time and/or preventative measures to take place. For example, through tracking task specific metrics during execution of the tasks, tasks may be classified and monitored for deviations to proactively and/or preventatively identify anomalies. Further, upon a detection of anomaly, the one or more main cores of the processor system to remove anomalous artefacts. Accordingly, the claims recite a real time process of anomaly detection, providing a practical application and as a whole, satisfy Step 2A, Prong Two. Therefore, Applicant respectfully requests withdrawal of this rejection,” (see pgs 6-7) examiner respectfully disagrees.
The claim recites, “classifying the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task; comparing the classified task with an expected completion profile of the task; determining, …, if the classified task deviates from the expected completion profile; and upon determining the classified task deviates from the expected completion profile, updating the task classification and identifying an anomaly in the nominal execution of the task, ” which under BRI, constitutes as mental processes as they can practically be performed in the human mind, or by a human using pen and paper as a physical aid (MPEP 2106.04(a)(2), subsection III). The additional steps of “executing a task on the processor system; monitoring, in real time via a dedicated communication means, hardware performance monitors, HPMs, of at least one resource of the processor system resulting from the execution of the task on the processor system; receiving, at an anomaly detector that is in direct communication with one or more main cores of the processor system, one or more signals indicative of the task being executed; responsive to receiving the one or more signals, tracking, via the anomaly detector, task specific metrics that are generated by the task; feeding task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task;” represent insignificant extra-solution activity of data gathering and data outputting (MPEP 2106.05(g)). They can also represent mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). Also, the additional step of “upon identifying the anomaly in the nominal execution of the task, instructing and causing an interruption to one or more main cores of the processor system in order to remove an anomalous artefact” represents insignificant extra-solution activity under (MPEP 2106.05(g)) and/or mere instruction to apply an exception (MPEP 2106.05(f)). The limitation of instructing and causing an interruption to one or more main cores merely constitutes a generic response to the result of the abstract analysis identifying a problem (ie anomaly). It is well-known, routine and conventional to cause an interrupt in response detecting a problem (see Microsoft Computer Dictionary (2002) definition for “interrupt”). Argument is moot. Examiner maintains his rejection.
With respect to applicant’s argument, “For example, Freitag contains no disclosure, teaching, or suggestion of one or more main cores sending signals indicative of the task being executed, and as such, cannot therefore teach that the signal is indicative of the task being executed for tracking task specific metrics associated with the task. While Freitag briefly discusses that in response to the monitored applications not behaving as expected, the evaluating logic 22 can output a control signal to a processor to request evaluating logic. Freitag [0039]. However, this is reactionary process is not analogous to the proactive steps recited in the amended claims,” (see Remarks pgs 9-10) examiner respectfully disagrees.
The claim recites “receiving, at an anomaly detector …, one or more signals indicative of the task being executed.” Freitag [0034] describes applications A executing on a processor and hardware performance counters that track performance events indicative of task execution. Freitag (Figs. 1-2 and ¶¶ 35-36) further discloses that data from the hardware performance counters is transmitted externally via data interface D to monitoring processor 20, which corresponds to the anomaly detector, thereby teaching receipt of one or more signals indicative of the task being executed. Argument is moot. Examiner maintains his rejection.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4,6-8 and 10-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites “metrics that are generated by the task” (see line 11), which is not clear. Tasks cause measurements or performance data to be generated and the system derives metrics from the task’s execution. Metrics are generated by a system from the task’s execution, not directly by the task itself. Furthermore, the claim recites “the classified task” (see lines 16,18, and 20) and “the task classification” (see line 21), which lacks antecedent basis. The claim previously recites “classifying the task” in line 12 of claim and again in line 13 of claim. It is unclear whether “the classified task” and “the task classification” is referring to one of the instances or something else.
Claim 10 recites similar claim limitations and is rejected under the same rationale.
The remaining claims, not specifically mentioned, are dependent claims and rejected for inheriting the deficiency of one of the claims listed above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of
matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the
conditions and requirements of this title.
Claims 1-4,6-8 and 10-16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without any additional elements that integrate the abstract into a
practical application, or amount to significantly more than the abstract idea.
Step 1:
Claims 1-4 and 6-8 are directed to a method, which falls within the statutory category of process.
Claims 10-16 are directed to a system, comprising a processor system and means for detecting anomalies, which falls within the statutory category of machine.
Claim 1:
Step 2A Prong 1: The claim recites a method for detecting anomalies in a nominal execution of tasks in a processor system, the method comprising:
“classifying the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task;
comparing the classified task with an expected completion profile of the task;
determining, …, if the classified task deviates from the expected completion profile; and
upon determining the classified task deviates from the expected completion profile, updating the task classification and identifying an anomaly in the nominal execution of the task”.
These steps, under BRI, constitutes as mental processes as they can practically be
performed in the human mind, or by a human using pen and paper as a physical aid (MPEP 2106.04(a)(2), subsection III).
Step 2A Prong 2 and Step 2B: The claim recites the additional elements:
“executing a task on the processor system;
monitoring, in real time via a dedicated communication means, hardware performance monitors, HPMs, of at least one resource of the processor system resulting from the execution of the task on the processor system;
receiving, at an anomaly detector that is in direct communication with one or more main cores of the processor system, one or more signals indicative of the task being executed;
responsive to receiving the one or more signals, tracking, via the anomaly detector, task specific metrics that are generated by the task;
feeding task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task;”
These additional steps represent insignificant extra-solution activity of data gathering and data outputting (MPEP 2106.05(g)). They can also represent mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)).
“upon identifying the anomaly in the nominal execution of the task, instructing and causing an interruption to one or more main cores of the processor system in order to remove an anomalous artefact.”
This additional step represents insignificant extra-solution activity under (MPEP 2106.05(g)) and/or mere instruction to apply an exception (MPEP 2106.05(f)). The limitation of instructing and causing an interruption to one or more main cores merely constitutes a generic response to the result of the abstract analysis identifying a problem (ie anomaly). It is well-known, routine and conventional to cause an interrupt in response detecting a problem (see Microsoft Computer Dictionary (2002) definition for “interrupt”)
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 2 recites:
“wherein the processor system comprises at least one of: a single core system or a multi-core system-on-chip, SoC, system”, which further describes the processor system. This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). This can also represent generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 3 recites:
“wherein the steps of monitoring, classifying, comparing and identifying are performed by a tightly coupled hardware accelerator, TCHA”, which describes the device performing the steps. This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). This can also represent generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 4 recites:
“wherein the processor system is based on a customisable instruction set architecture, ISA, configured to instruct the TCHA”, which further describes the processor system. This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). This can also represent generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 6 recites:
“upon identifying the anomaly in the nominal execution of the task, notifying one or more main cores of the processor system.” This represents insignificant extra-solution activity of data outputting (MPEP 2106.05(g)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 7 recites:
“wherein the comparing the classified task with the expected completion profile of the task and identifying anomalies is performed by at least one of procedural coding or machine learning paradigms” This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). The Federal Circuit held that “patents that do no more than claim the application of generic machine learning to new data environments without disclosing improvements to the machine learning models to be applied, are patent ineligible under § 101.” Recentive Analytics, Inc. v. Fox Corp.
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 8 recites:
“inputting historical HPM data for the completion of the task into a machine learning model in order to determine the expected completion profile of the task”. This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). The Federal Circuit held that “patents that do no more than claim the application of generic machine learning to new data environments without disclosing improvements to the machine learning models to be applied, are patent ineligible under § 101.” Recentive Analytics, Inc. v. Fox Corp.
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 10:
Step 2A Prong 1: The claim recites a system comprising:
"classify the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task;
compare the classified task with an expected completion profile of the task;
determine , …, if the classified task deviates from the expected completion profile; and
upon determining the classified task deviates from the expected completion profile, update the task classification and identify an anomaly in the nominal execution of the task.”
These steps, under BRI, constitutes as mental processes as they can practically be
performed in the human mind, or by a human using pen and paper as a physical aid (MPEP 2106.04(a)(2), subsection III).
Step 2A Prong 2 and Step 2B: The claim recites the additional elements:
“a processor system; and a means for detecting anomalies in a nominal execution of tasks in the processor system, wherein the means for detecting the anomalies is connected to the processor system via a dedicated communication means and being configured to”. These elements represent mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)).
“monitor, in real time via the dedicated communication means, hardware performance monitors, HPMs, of at least one resource of the processor system resulting from the execution of a task on the processor system;
receiving, at an anomaly detector that is in direct communication with one or more main cores of the processor system, one or more signals indicative of the task being executed;
responsive to receiving the one or more signals, track, via the anomaly detector, task specific metrics that are generated by the task;
feed task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task”
These represent insignificant extra-solution activity of data gathering and data outputting (MPEP 2106.05(g)).
“upon identifying the anomaly in the nominal execution of the task, instruct and cause an interruption to one or more main cores of the processor system in order to remove an anomalous artefact.”
This represents insignificant extra-solution activity under (MPEP 2106.05(g)) and/or mere instruction to apply an exception (MPEP 2106.05(f)). The limitation of instructing and causing an interruption to one or more main cores merely constitutes a generic response to the result of the abstract analysis identifying a problem (ie anomaly). It is well-known, routine and conventional to cause an interrupt in response detecting a problem (see Microsoft Computer Dictionary (2002) definition for “interrupt”)
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 11 recites:
“wherein the processor system is a single core system or a multi-core system-on-chip, SoC, system”, which further describes the processor system. This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). This can also represent generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 12 recites:
“wherein the processor system is based on a customisable instruction set architecture, ISA, configured to instruct the means for detecting the anomalies”, which further describes the processor system. This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). This can also represent generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 13 recites:
“wherein the means for detecting the anomalies comprises a tightly coupled hardware accelerator, TCHA, tightly coupled to the processor system”, which describes the device performing the means. This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). This can also represent generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 14 recites:
“means for at least one of interrupting or notifying one or more main cores of the processor system when the anomaly is detected.” This represents insignificant extra-solution activity of data outputting (MPEP 2106.05(g)). This also represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 15 recites:
“wherein the processor system is a processor system for use on an aircraft”. This represents generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim 16 recites:
“wherein the TCHA comprises a machine learning model configured to classify the task.” This represents mere instruction to apply the exception on a generic computer (MPEP 2106.05(f)). The Federal Circuit held that “patents that do no more than claim the application of generic machine learning to new data environments without disclosing improvements to the machine learning models to be applied, are patent ineligible under § 101.” Recentive Analytics, Inc. v. Fox Corp.
The claim does not disclose any additional limitations that integrate the abstract idea into
a practical application, nor amount to significantly more than the abstract idea. The claim is therefore ineligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,6-8,10,11,and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Freitag et al. (US 2018/0060147) in view of Rao et al. (US 2012/0180061) and in further view of Tuncer “Online Diagnosis of Performance Variation in HPC Systems Using Machine Learning”.
Regarding Claim 1, Freitag teaches a method for detecting anomalies in a nominal execution of tasks in a processor system, the method comprising:
executing a task on the processor system (Fig 1-2 item 100 and [0033]-[034]);
monitoring, in real time ([0038]) via a dedicated communication means (Fig 1-2 item D and [0035],[0043]), hardware performance monitors, HPMs, of at least one resource of the processor system resulting from the execution of the task on the processor system ([0034]-[0035]]);
receiving, at an anomaly detector (Fig 1-2 item 20 and [0036]) that is in direct communication (Fig 1-2 item D and [0035],[0043]) with one or more main cores of the processor system, one or more signals indicative of the task being executed ([0035]-[0036]);
responsive to receiving the one or more signals, tracking, via the anomaly detector, task specific metrics that are generated by the task ([0036] “target performance profiles”) .
comparing the classified task with an expected completion profile of the task ([0038],[0047]);
determining, …, if the classified task deviates from the expected completion profile ([0038]); and
upon determining the classified task deviates from the expected completion profile, updating the classification and identifying an anomaly in the nominal execution of the task ([0038]).
upon identifying the anomaly in the nominal execution of the task, instructing and causing an interruption to one or more main cores of the processor system in order to remove an anomalous artefact ([0039]).
Freitag further teaches classifying the task based on the monitored HPMs as abnormal ([0038]). However, Freitag does not explicitly teach classifying the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task.
Rao teaches classifying the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task ([0006], “Task are classified as either memory bound or CPU bound”, which is understood to be based on Arithmetic Intensity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Freitag and Rao, to classify the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task. A person of ordinary skill in the art could have been motivated to combine the teachings it would optimize task placement, improving fair execution time of all tasks and reduced power consumed (Rao, [0175]).
Furthermore, Freitag does not explicitly teach feeding task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task, wherein the machine learning model determines if the classified task deviates from the expected completion profile.
Tuncer teaches feeding task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task, wherein the machine learning model determines if the classified task deviates from the expected completion profile (Introduction Paragraph 4, “… Our framework detects and diagnoses anomalies by applying machine learning algorithms on resource usage and performance metrics; 3 Anomaly Detection and Diagnosis Paragraph 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Freitag, Rao, and Tuncer to feed task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task, wherein the machine learning model determines if the classified task deviates from the expected completion profile. A person of ordinary skill in the art could have been motivated to combine the teachings to provide efficient operations of HPC systems, reducing delayed mitigation wasted computing resources (Tuncer, Introduction Paragraph 3).
Regarding Claim 2, Freitag in view of Rao and Tuncer teaches the method of claim 1. Freitag further teaches wherein the processor system comprises at least one of: a single core system or a multi-core system-on-chip, SoC, system (Fig 1-2,[0034], [0041]).
Regarding claim 6, Freitag in view of Rao and Tuncer teaches the method of claim 1. Freitag further teaches comprising: upon identifying the anomaly in the nominal execution of the task, notifying one or more main cores of the processor system ([0039]).
Regarding claim 7, Freitag in view of Rao and Tuncer teaches method of claim 1. Furthermore, Tuncer teaches wherein the comparing the classified task with the expected completion profile of the task and identifying anomalies is performed by at least one of procedural coding or machine learning paradigms (Introduction Paragraph 4, “… Our framework detects and diagnoses anomalies by applying machine learning algorithms on resource usage and performance metrics).
Regarding claim 8, Freitag in view of Rao and Tuncer teaches method of claim 1. Furthermore, Tuncer teaches inputting historical HPM data for the completion of the task into a machine learning model in order to determine the expected completion profile of the task (3 Anomaly Detection and Diagnosis Paragraph 2, “To detect and classify anomalies, we propose an automated approach based on machine learning… We leverage historical resource usage and performance data that are collected from healthy and anomalous nodes to learn the signatures of target anomalies”).
Regarding claim 10, Freitag discloses a system comprising:
a processor system; and a means for detecting anomalies in a nominal execution of tasks in the processor system, wherein the means for detecting the anomalies is connected to the processor system via a dedicated communication means (Fig 1-2 and [0033],[0034],[0043]) and configured to:
monitor, in real time ([0038]) via the dedicated communication means (Fig 1-2 item D and [0035],[0043]), hardware performance monitors, HPMs, of at least one resource of the processor system resulting from the execution of the task on the processor system ([0034]-[0035]]);
receive, at an anomaly detector (Fig 1-2 item 20 and [0036]) that is in direct communication (Fig 1-2 item D and [0035],[0043]) with one or more main cores of the processor system, one or more signals indicative of the task being executed ([0035]-[0036]);
responsive to receiving the one or more signals, track, via the anomaly detector, task specific metrics that are generated by the task ([0036] “target performance profiles”) .
compare the classified task with an expected completion profile of the task ([0038],[0047]);
determine, …, if the classified task deviates from the expected completion profile ([0038]); and
upon determining the classified task deviates from the expected completion profile, update the task classification and identify an anomaly in the nominal execution of the task ([0038]).
upon identifying the anomaly in the nominal execution of the task, instruct and cause an interruption to one or more main cores of the processor system in order to remove an anomalous artefact ([0039]).
Freitag further teaches classifying the task based on the monitored HPMs as abnormal ([0038]). However, Freitag does not explicitly teach to classify the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task.
Rao teaches to classify the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task ([0006], “Task are classified as either memory bound or CPU bound”, which is understood to be based on Arithmetic Intensity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Freitag and Rao, to classify the task based on the monitored HPMs, wherein the task is classified based on an Arithmetic Intensity, Al, metric of the task. A person of ordinary skill in the art could have been motivated to combine the teachings it would optimize task placement, improving fair execution time of all tasks and reduced power consumed (Rao, [0175]).
Furthermore, Freitag does not explicitly teach feed task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task, wherein the machine learning model determines if the classified task deviates from the expected completion profile.
Tuncer teaches feeding task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task, wherein the machine learning model determines if the classified task deviates from the expected completion profile (Introduction Paragraph 4, “… Our framework detects and diagnoses anomalies by applying machine learning algorithms on resource usage and performance metrics; 3 Anomaly Detection and Diagnosis Paragraph 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Freitag, Rao, and Tuncer to feed task specific metrics that are tracked by the anomaly detector to one or more machine learning models for classifying the task, wherein the machine learning model determines if the classified task deviates from the expected completion profile. A person of ordinary skill in the art could have been motivated to combine the teachings to provide efficient operations of HPC systems, reducing delayed mitigation wasted computing resources (Tuncer, Introduction Paragraph 3).
Regarding 11, Freitag in view of Rao and Tuncer teaches the system of claim 10. Freitag further teaches wherein the processor system comprises at least one of: a single core system or a multi-core system-on-chip, SoC, system (Fig 1-2,[0034], [0041]).
Regarding 14, Freitag in view of Rao and Tuncer teaches the system of claim 10. Freitag further teaches means for at least one of interrupting or notifying one or more main cores of the processor system when the anomaly is detected ([0039]).
Regarding 15, Freitag in view of Rao and Tuncer teaches the method of claim 10. Freitag further teaches wherein the processor system is a processor system for use on an aircraft ([0033]).
Claims 3,4,12,13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over
Freitag in view of Rao and Tuncer, and in further view of Fritzmann “RISQ-V_ Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography”.
Regarding Claim 3, Freitag in view of Rao and Tuncer teaches method of claim 1. However, Freitag in view of Rao and Tuncer does not explicitly teach wherein the steps of monitoring, classifying, comparing and identifying are performed by a tightly coupled hardware accelerator, TCHA.
Fritzmann teaches a tightly coupled hardware accelerator, TCHA (Abstract, “…RISQ-V, an enhanced RISC-V architecture that integrates a set of powerful tightly coupled accelerators …”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Freitag, Rao, Tuncer, and Fritzmann wherein the steps of monitoring, classifying, comparing and identifying are performed by a tightly coupled hardware accelerator, TCHA. A person of ordinary skill in the art could have been motivated to combine the teachings to significantly increase the performance while keeping the silicon area overhead low (Fritzmann, Abstract).
Regarding Claim 4, Freitag in view of Rao, Tuncer, and Fritzmann teaches the method of claim 3. Fritzmann further teaches wherein the processor system is based on a customisable instruction set architecture, ISA, configured to instruct the TCHA (Introduction Paragraph 4, “RISC-V is a free and open ISA… RISC-V allows for the development of open source hardware with hardware security extensions …”).
Regarding Claim 12, Freitag in view of Rao and Tuncer teaches the system of claim 10. However, Freitag in view of Rao and Tuncer does not explicitly teach wherein the processor system is based on a customisable instruction set architecture, ISA, configured to instruct the means for detecting the anomalies.
Fritzmann teaches wherein the processor system is based on a customisable instruction set architecture, ISA (Introduction Paragraph 4, “RISC-V is a free and open ISA… RISC-V allows for the development of open source hardware with hardware security extensions …”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Freitag, Rao, Tuncer and Fritzmann wherein the processor system is based on a customisable instruction set architecture, ISA, configured to instruct the means for detecting the anomalies. A person of ordinary skill in the art could have been motivated to combine the teachings to significantly increase the performance while keeping the silicon area overhead low (Fritzmann, Abstract).
Regarding Claim 13, Freitag in view of Rao and Tuncer teaches system of claim 10. However, Freitag in view of Rao and Tuncer does not explicitly teach wherein the means for detecting the anomalies comprises a tightly coupled hardware accelerator, TCH, tightly coupled to the processor system.
Fritzmann teaches a tightly coupled hardware accelerator, TCHA (Abstract, “…RISQ-V, an enhanced RISC-V architecture that integrates a set of powerful tightly coupled accelerators …”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Freitag, Rao, Tuncer, and Fritzmann wherein the means for detecting the anomalies comprises a tightly coupled hardware accelerator, TCH, tightly coupled to the processor system. A person of ordinary skill in the art could have been motivated to combine the teachings to significantly increase the performance while keeping the silicon area overhead low (Fritzmann, Abstract).
Regarding 16, Freitag in view of Rao, Tuncer and Fritzmann teaches the system of claim 13. Tuncer further teaches a machine learning model configured to classify the task (3 Anomaly Detection and Diagnosis Paragraph 2, “To detect and classify anomalies, we propose an automated approach based on machine learning”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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