DETAILED ACTION
This action is responsive to the communication filed 16 April 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Group I Species 1 (FIG. 3) embodiment in the reply filed on 16 April 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication No. 2017/0256634 (published Sept. 7, 2017) (hereinafter “Matsuura 1”).
Regarding independent claim 1, Matsuura 1 discloses: A semiconductor device (FIG. 20, depicting a semiconductor device, [0140]) comprising:
a semiconductor substrate of a first conductivity type (FIG. 20, semiconductor substrate SS having various regions including regions having N and P types, [0065]) having an upper surface (FIG. 20, surface Sa, [0066]) and a lower surface (FIG. 20, surface Sb, [0065]);
a first trench (FIG. 20, e.g., leftmost trench T1, [0060]), a second trench (FIG. 20, e.g., second from leftmost trench T1), a third trench (FIG. 20, e.g., leftmost trench T2, [0060]), and a fourth trench (FIG. 20, e.g., second from leftmost trench T2) which are formed in the semiconductor substrate on the upper surface side of the semiconductor substrate (FIG. 20, depicting wherein the trenches T1/T2 are formed in the semiconductor substrate SS on the surface Sa side of the semiconductor substrate SS);
a first gate electrode formed in the first trench (FIG. 20, trench gate electrode TG1 formed in the leftmost trench T1, [0042]) with a first gate insulating film interposed between the first gate electrode and the first trench (FIG. 20, gate insulating film GI interposed between the leftmost trench T1 and the trench gate electrode TG1 formed therein, [0083]);
a second gate electrode formed in the second trench (FIG. 20, trench gate electrode TG1 formed in the second from leftmost trench T1, [0042]) with a second gate insulating film interposed between the second gate electrode and the second trench (FIG. 20, gate insulating film GI interposed between the second from leftmost trench T1 and the trench gate electrode TG1 formed therein);
a third gate electrode formed in the third trench (FIG. 20, trench gate electrode TG2 formed in the leftmost trench T2, [0047]) with a third gate insulating film interposed between the third gate electrode and the third trench (FIG. 20, gate insulating film GI interposed between the leftmost trench T2 and the trench gate electrode TG2 formed therein);
a fourth gate electrode formed in the fourth trench (FIG. 20, trench gate electrode TG2 formed in the second from leftmost trench T2, [0047]) with a fourth gate insulating film interposed between the fourth gate electrode and the fourth trench (FIG. 20, gate insulating film GI interposed between the second from leftmost trench T2 and the trench gate electrode TG2 formed therein);
a first hole barrier region of the first conductivity type (FIG. 20, e.g., leftmost N-type hole barrier region NHB, [0071]) formed in the semiconductor substrate between the first trench and the second trench on the upper surface side of the semiconductor substrate (FIG. 20, depicting wherein the leftmost N-type hole barrier region NHB is formed in the semiconductor substrate SS between the leftmost and second from leftmost trenches T1 on the surface Sa side of the semiconductor substrate SS);
a first base region of a second conductivity type which is an opposite conductivity type to the first conductivity type (FIG. 20, e.g., P-type body region PB between the leftmost and second from leftmost trenches T1, [0066]), the first base region being formed in the first hole barrier region (FIG. 20, depicting wherein the P-type body region PB between the leftmost and second from leftmost trenches T1 is formed in the same region as the leftmost N-type hole barrier region NHB);
an emitter region of the first conductivity type formed in the first base region (FIG. 20, e.g., N+-type emitter region NE formed in the same region as the P-type body region PB between the leftmost and second from leftmost trenches T1, [0044]);
a second hole barrier region of the first conductivity type (FIG. 20, e.g., second from leftmost N-type hole barrier region NHB, [0071]) formed in the semiconductor substrate between the third trench and the fourth trench on the upper surface side of the semiconductor substrate (FIG. 20, depicting wherein the second from leftmost N-type hole barrier region NHB is formed in the semiconductor substrate SS between the leftmost and second from leftmost trenches T2 on the surface Sa side of the semiconductor substrate SS);
a second base region of the second conductivity type (FIG. 20, e.g., P-type body region PB between the leftmost and second from leftmost trenches T2, [0066]) formed in the second hole barrier region (FIG. 20, depicting wherein the P-type body region PB between the leftmost and second from leftmost trenches T2 is formed in the same region as the second from leftmost N-type hole barrier region NHB); and
a first floating region of the second conductivity type (FIG. 20, e.g., second from leftmost P-type floating region PF, [0054]) formed in the semiconductor substrate between the second trench and the third trench on the upper surface side of the semiconductor substrate (FIG. 20, depicting wherein the second from leftmost P-type floating region PF is formed in the semiconductor substrate SS between the second from leftmost trench T1 and the leftmost trench T2 on the surface Sa side of the semiconductor substrate SS),
wherein the first floating region covers a second bottom surface of the second trench (FIG. 20, depicting wherein the second from leftmost P-type floating region PF covers the bottom surface of the second from leftmost trench T1), and covers a third bottom surface of the third trench (FIG. 20, depicting wherein the second from leftmost P-type floating region PF covers the bottom surface of the leftmost trench T2) so as to reach the semiconductor substrate between the third trench and the fourth trench (FIG. 20, depicting wherein the second from leftmost P-type floating region PF reaches at least a portion of the semiconductor substrate SS between the leftmost trench T2 and the second from leftmost trench T2), and
wherein a first distance between the second base region and the first floating region (FIG. 20, depicting, e.g., a first distance, wherein the first distance extends from a bottommost surface of the P-type body region PB between the leftmost and second from leftmost trenches T2 to the topmost surface of the second from leftmost P-type floating region PF) is smaller than a second distance between the first base region and the first floating region (FIG. 20, depicting, e.g., a second distance, wherein the second distance extends from a topmost surface of the P-type body region PB between the leftmost and second from leftmost trenches T1 to the topmost surface of the second from leftmost P-type floating region PF, further depicting wherein the first distance is smaller than the second distance).
Regarding claim 2, Applicant further claims wherein “an impurity concentration of the second hole barrier region at a first portion in a vicinity of a boundary between the first floating region and the second hole barrier region in the second hole barrier region is lower than an impurity concentration of the first hole barrier region at a same depth as the first portion.”
When the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. MPEP § 2112.01(I). “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” Id. (citing In re Best, 562 F.2d 1252, 1255, 195 U.S.P.Q. 430, 433 (C.C.P.A. 1977)). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” Id. (quoting In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)). “Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product.” Id. (citing In re Best, 562 F.2d at 1255).
In the instant case, Matsuura 1 discloses a semiconductor device structure that is identical to the display device structure claimed in Applicant’s claim 1, noted above in the rejection of independent claim 1, and thus necessarily possesses the properties of the display device structure claimed in Applicant’s claim 2, including wherein an impurity concentration of the second hole barrier region at a first portion in a vicinity of a boundary between the first floating region and the second hole barrier region in the second hole barrier region is lower than an impurity concentration of the first hole barrier region at a same depth as the first portion.
Accordingly, Matsuura 1 discloses a semiconductor device that necessarily possesses the properties of the semiconductor device structure disclosed in Applicant’s claim 2, and thus anticipates claim 2.
Regarding claim 3, Matsuura 1 further discloses wherein the first trench (FIG. 20, leftmost trench T1) has a first side surface, a second side surface that is opposed to the first side surface, and a first bottom surface connecting the first side surface to the second side surface (FIG. 20, depicting wherein the leftmost trench T1 has a first, left side surface, a second, right side surface, and a bottom surface connecting the first, left and second, right side surfaces),
wherein the second trench (FIG. 20, second from leftmost trench T1) has a third side surface, a fourth side surface that is opposed to the third side surface, and the second bottom surface connecting the third side surface to the fourth side surface (FIG. 20, depicting wherein the second from leftmost trench T1 has a first, left side surface, a second, right side surface, and a bottom surface connecting the first, left and second, right side surfaces),
wherein the third trench (FIG. 20, leftmost trench T2) has a fifth side surface, a sixth side surface that is opposed to the fifth side surface, and the third bottom surface connecting the fifth side surface to the sixth side surface (FIG. 20, depicting wherein the leftmost trench T2 has a first, left side surface, a second, right side surface, and a bottom surface connecting the first, left and second, right side surfaces),
wherein the fourth trench has a seventh side surface, an eighth side surface that is opposed to the seventh side surface, and a fourth bottom surface connecting the seventh side surface to the eighth side surface (FIG. 20, depicting wherein the second from leftmost trench T2 has a first, left side surface, a second, right side surface, and a bottom surface connecting the first, left and second, right side surfaces),
wherein the first trench and the second trench are provided to be spaced from each other such that the second side surface and the third side surface are adjacent to each other (FIG. 20, depicting wherein the leftmost and second from leftmost trenches T1 are provided to be spaced from each other such that the second, right surface of the leftmost trench T1 and the first, left surface of the second from leftmost trench T1 are adjacent to each other),
wherein the third trench and the fourth trench are provided to be spaced from each other such that the sixth side surface and the seventh side surface are adjacent to each other (FIG. 20, depicting wherein the leftmost and second from leftmost trenches T2 are provided to be spaced from each other such that the second, right surface of the leftmost trench T2 and the first, left surface of the second from leftmost trench T2 are adjacent to each other),
wherein the first floating region (FIG. 20, second from leftmost P-type floating region PF, [0054]) is formed in the semiconductor substrate between the fourth side surface and the fifth side surface (FIG. 20, depicting wherein the second from leftmost P-type floating region PF is formed in the semiconductor substrate SS between the second, right surface of the second from leftmost trench T1 and the first, left surface of the leftmost trench T2), and covers the third bottom surface so as to extend beyond the sixth side surface (FIG. 20, depicting wherein the second from leftmost P-type floating region PF covers the bottom surface of the leftmost trench T2 and extends beyond the second, right surface of the leftmost trench T2),
wherein the second distance is a distance along the third side surface (FIG. 20, depicting wherein the second distance extending from a topmost surface of the P-type body region PB between the leftmost and second from leftmost trenches T1 to the topmost surface of the second from leftmost P-type floating region PF is a distance along a first, left surface of the second from leftmost trench T1), and
wherein the first distance is a distance along the sixth side surface (FIG. 20, depicting wherein the first distance extending from a bottommost surface of the P-type body region PB between the leftmost and second from leftmost trenches T2 to the topmost surface of the second from leftmost P-type floating region PF is a distance along the second, right surface of the leftmost trench T2).
Regarding claim 7, Matsuura 1 further discloses an interlayer insulating film (FIG. 20, interlayer insulating film IL, [0075]) formed over the upper surface of the semiconductor substrate so as to cover the first trench, the second trench, the third trench, and the fourth trench (FIG. 20, depicting wherein the interlayer insulating film IL covers all of the trenches T1/T2);
a gate wiring (FIG. 19, gate line GL, [0038]) and an emitter electrode (FIGS. 19/20, emitter electrode EE, [0038]) formed on the interlayer insulating film (FIGS. 19/20, depicting wherein the gate line GL and the emitter electrode EE are formed on the interlayer insulating film IL);
a collector region of the second conductivity type (FIG. 20, P+-type collector region PC, [0065]) formed in the semiconductor substrate on the lower surface side of the semiconductor substrate (FIG. 20, depicting wherein the P+-type collector region PC is formed in the semiconductor substrate SS on the surface Sb side of the semiconductor substrate SS); and
a collector electrode (FIG. 20, collector electrode CE, [0065]) formed under the lower surface of the semiconductor substrate (FIG. 20, depicting wherein the collector electrode CE is formed under the surface Sb of the semiconductor substrate SS),
wherein the first gate electrode is electrically connected to the gate wiring (FIGS. 19/20, depicting wherein the trench gate electrode TG1 formed in the leftmost trench T1 is electrically connected to the gate line GL),
wherein the emitter region, the first base region, the second gate electrode, and the second base region are electrically connected to the emitter electrode (FIGS. 19/20, depicting wherein the N+-type emitter region NE formed in the same region as the P-type body region PB between the leftmost and second from leftmost trenches T1, the P-type body region PB between the leftmost and second from leftmost trenches T1, the trench gate electrode TG1 formed in the second from leftmost trench T1, and the P-type body region PB between the leftmost and second from leftmost trenches T2 are electrically connected to the emitter electrode EE), and
wherein the collector region is electrically connected to the collector electrode (FIGS. 19/20, depicting wherein the P+-type collector region PC is electrically connected to the collector electrode CE).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura 1 in view of U.S. Patent Publication No. 2016/0359026 (published Dec. 8, 2016) (hereinafter “Matsuura 2”).
Regarding claim 4, Matsuura 1 further discloses wherein a second floating region of the second conductivity type (FIG. 20, e.g., third from leftmost P-type floating region PF, [0054]) formed in the semiconductor substrate on the eighth side surface side, on the upper surface side of the semiconductor substrate (FIG. 20, depicting wherein the third from leftmost P-type floating region PF is formed in the semiconductor substrate SS on the second, right side of the second from leftmost trench T2, on the surface Sa side of the semiconductor substrate SS); and
a third floating region of the second conductivity type (FIG. 20, e.g., leftmost P-type floating region PF, [0054]) formed in the semiconductor substrate on the first side surface side, on the upper surface side of the semiconductor substrate (FIG. 20, depicting wherein the leftmost P-type floating region PF is formed in the semiconductor substrate SS on the first, left side of the leftmost trench T1, on the surface Sa side of the semiconductor substrate SS),
wherein the third floating region covers the first bottom surface (FIG. 20, depicting wherein the leftmost P-type floating region PF covers the bottom surface of the leftmost trench T1),
wherein the second floating region covers the fourth bottom surface so as to extend beyond the seventh side surface (FIG. 20, depicting wherein the third from leftmost P-type floating region PF covers the bottom surface of the second from leftmost trench T2 and extends beyond the first, left side of the second from leftmost trench T2),
wherein the first floating region and the third floating region are spaced apart from each other (FIG. 20, depicting wherein the second from leftmost P-type floating region PF and the leftmost P-type floating region PF are spaced apart).
Matsuura 1 does not specifically disclose wherein the first floating region and the second floating region are in contact with each other.
In the same field of endeavor, Matsuura 2 discloses a semiconductor device (FIG. 29, IGBT element 4, [0140]) including a plurality of trenches and floating regions (FIG. 29, depicting trenches E1-E4 and P-type floating regions 36, [0141]), and further wherein the floating regions may have a configuration wherein the floating regions may be in contact with each other (FIG. 29, depicting wherein various P-type floating regions have a configuration where the P-type floating regions contact each other). Regarding the configuration of the floating regions, in [0143], Matsuura 2 states: “The P type floating region 36 of the configuration described above is formed using high energy implantation and, regardless of the shape of a surface, an injection part can be designed. Therefore, the P type floating region 36 of the above configuration has characteristic in that, as compared with the P type floating region 36 of the configuration shown in FIG. 1, a high level of pattern precision is not required, making it easier to manufacture the device. Furthermore, as compared with the case in FIG. 1, freedom of arrangement thereof in a plane of the semiconductor substrate 64 increases (a specific example of the arrangement will be explained in Fifth Embodiment).”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of Matsuura 1 by substituting the P-type floating region configuration of Matsuura 2 for the configuration of the second from leftmost and third from leftmost P-type floating regions PF depicted in Matsuura 1 in order to improve manufacturing ease of the semiconductor device. See Matsuura 2 [0143].
Regarding claim 5, Matsuura 1 in view of Matsuura 2 further discloses wherein a distance between the sixth side surface and the seventh side surface (FIG. 20, depicting, e.g., a third distance, wherein the third distance extends from a second, right side of the leftmost trench T2 to a first, left side of the second from leftmost trench T2) is shorter than a distance between the second side surface and the third side surface (FIG. 20, depicting, e.g., a fourth distance, wherein the fourth distance extends from a second, right side of the leftmost trench T1 to a first, left side of the second from leftmost trench T1, further depicting wherein the third distance is shorter than the fourth distance).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2020/0066887 (published Feb. 27, 2020) (disclosing a trench and floating diffusion region configuration similar to that of the instant application); 2012/0313139 (published May 14, 2012) (disclosing a trench and floating diffusion region configuration similar to that of the instant application); 2017/0236927 (published Aug. 17, 2017) (disclosing a floating diffusion region configuration similar to that of the instant application).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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