DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 26 June 2026. Claims 1-20 are pending in this application. Claims 10-14 are withdrawn from consideration, and Claims 1-9, 15-20 are examined ion this Office Action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 3 and Subspecies 1 in the reply filed on 26 June 2026 is acknowledged. The traversal is on the ground(s) that that there is no search or examination burden. This is not found persuasive because each of the species and subspecies require different geometries. It would be unlikely that a single reference would cover the multiple different configurations. Therefore, there would be a significant burden since the examiner would have to search separately for each configuration.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 15-17, 20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Suzuki et. al (US 2020/0027958 A1).
Regarding Claim 1, Suzuki discloses (as shown in Fig. 1) An electronic device, comprising:
a substrate; ([0053] The active matrix substrate 100A includes a substrate 1)
and a driving element ([0053] thin film transistors (TFTs) 10) disposed on the substrate (1), ([0053] The active matrix substrate 100A includes … a plurality of thin film transistors (TFTs) 10 supported on the substrate 1)
the driving element (10) comprising a refractive index matching structure ([0065] gate insulating layer 12),
the refractive index matching structure (12) comprising a first layer ([0068] silicon oxide layer 12a), a second layer ([0068] silicon nitride layer 12b) and a first refractive index matching layer ([0068] intermediate layer 12c), ([0068] In this embodiment, the gate insulating layer 12 further includes an intermediate layer 12c disposed between the silicon oxide layer 12a and the silicon nitride layer 12b, as illustrated in FIG. 1)
wherein the first refractive index matching layer (12c) is disposed between the first layer (12a) and the second layer (12b), ([0068] In this embodiment, the gate insulating layer 12 further includes an intermediate layer 12c disposed between the silicon oxide layer 12a and the silicon nitride layer 12b, as illustrated in FIG. 1)
and a refractive index of the first refractive index matching layer (12c) is in a range between a refractive index of the first layer (12a) and a refractive index of the second layer (12b). ([0068] The intermediate layer 12c has a refractive index nC higher than a refractive index nA of the silicon oxide layer 12a and lower than a refractive index nB of the silicon nitride layer 12b)
Regarding Claim 2, Suzuki further discloses (as shown in Fig. 1) wherein the driving element comprises:
a first conductive layer comprising a gate electrode; ([0055] Each of the plurality of TFTs 10 includes a gate electrode 11)
and a second conductive layer comprising a drain electrode, ([0055] [0055] Each of the plurality of TFTs 10 includes … a drain electrode 15)
wherein the refractive index matching structure (12) is disposed between the first conductive layer (11) and the second conductive layer (15). (See Fig. 1, showing the laminated gate insulating layer 12 between the gate electrode 11 and the drain electrode 15)
Regarding Claim 15, Suzuki further discloses (as shown in Fig. 1) wherein the first refractive index matching layer (12c) comprises silicon oxynitride, silicon oxide, silicon nitride, magnesium fluoride, calcium fluoride, barium fluoride, lanthanum fluoride, or combination thereof. ([0076] As the intermediate layer 12c, for example, a silicon oxynitride (SiOxNy: x may be greater than or equal to y, or x may be less than y) layer can be suitably used)
Regarding Claim 16, Suzuki further discloses (as shown in Fig. 1) wherein a thickness of the first refractive index matching layer (12c) ranges from 200 angstroms to 4000 angstroms. ([0098] The thickness of the silicon oxynitride layer 12c is, for example, 10 nm or more and 100 nm or less, 10 nm = 100 Angstroms, 100 nm = 1000 Angstroms)
Regarding Claim 17, Suzuki further discloses (as shown in Fig. 1) wherein a thickness of the first refractive index matching layer (12c) ranges from 200 angstroms to 3000 angstroms. ([0098] The thickness of the silicon oxynitride layer 12c is, for example, 10 nm or more and 100 nm or less, 10 nm = 100 Angstroms, 100 nm = 1000 Angstroms)
Regarding Claim 20, Suzuki further discloses (as shown in Fig. 1) wherein the driving element comprises a thin film transistor. ([0012] An active matrix substrate according to an embodiment of the present invention is an active matrix substrate including a substrate, a plurality of thin film transistors)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki as applied to claim 2 above, and further in view of Yang et. al (US 2016/0209691 A1).
Regarding Claim 3, Suzuki further discloses (as shown in Fig. 12) wherein the electronic device further comprises:
a planarization layer ([0061] The organic insulating layer (planarization film) 21) disposed on the second conductive layer (15); ([0060] The inorganic insulating layer (passivation film) 20 covers the oxide semiconductor layer 13, the source electrode 14, and the drain electrode 15… [0061] The organic insulating layer (planarization film) 21 is disposed on the inorganic insulating layer 20.)
a pixel electrode ([0064] The pixel electrode 24) disposed on the planarization layer (21) ([0062] The common electrode 22 is disposed on the organic insulating layer 21… [0063] The dielectric layer 23 is disposed so as to cover the common electrode 22… [0064] The pixel electrode 24 is disposed on the dielectric layer 23 in each pixel.)
and electrically connected to the drain electrode (15); ([0064] The pixel electrode 24 is connected to the drain electrode 15 of the TFT 10)
and a second refractive index matching layer ([0111] As the intermediate layer 20c, a silicon oxynitride (SiOxNy: x may be greater than or equal to y, or x may be less than y) layer can be suitably used for the same reason as described for the intermediate layer 12c of the gate insulating layer 12. To sufficiently produce the effect of reducing tinge variation, the refractive index nA of the silicon oxide layer 20a, the refractive index nB of the silicon nitride layer 20b, and the refractive index nC of the intermediate layer 20c preferably satisfy the relation nA≤nC ≤0.93 nB)
However, Suzuki fails to disclose:
and a second refractive index matching layer disposed between the planarization layer (21) and the pixel electrode (24),
wherein a refractive index of the second refractive index matching layer is in a range between a refractive index of the planarization layer (21) and a refractive index of the pixel electrode (24).
Yang discloses (as shown in Figs. 7, 9, 11) a second refractive index matching layer disposed between the planarization layer ([0082] polymer sublayers … 230B) and the pixel electrode ([0060] Pixel electrodes 106), ([0075] If desired, graded index layers may be incorporated elsewhere in the layers of layer 56 (e.g., between layer 230 and layer 104′, between layer 104′ and layer 206, etc.))
wherein a refractive index of the second refractive index matching layer is in a range between a refractive index of the planarization layer (230B) and a refractive index of the pixel electrode (106). ([0067] A graded index layer may, for example, be sandwiched between first and second layers with respective first and second different index of refraction values. Portions of the graded index layer adjacent to the first layer may have an index of refraction that is equal to or nearly equal to the first index of refraction value. Portions of the graded index layer adjacent to the second layer may have an index of refraction that is equal or nearly equal to the second index of refraction value. There may be any suitable number of graded index layers in display 14 (e.g., one or more, two or more, three or more, four or more, etc.)) ([0075] If desired, graded index layers may be incorporated elsewhere in the layers of layer 56 (e.g., between layer 230 and layer 104′, between layer 104′ and layer 206, etc.))
Yang teaches that dielectric layers may be fabricated with stepped indices of refraction in order to minimize undesired color shifts and reflections due a difference in indices of refraction between layers. ([0064] As a result, there is a potential for index of refraction differences between adjacent layers to lead to undesired optical effects. For example, index of refraction differences may lead to undesired reflections of ambient light (e.g., when structures 260 are located in an upper layer of display 14). Index of refraction differences may also create thin-film interference filters that can impart undesired color shifts to backlight 44 (e.g., when display 14 is being viewed by viewer 48 at a non-zero angle with respect to the surface normal of the display).) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have stepped graded refractive index layers between the planarization layer 230 and the common electrode layer 104’ (which is between the planarization layer 230 and the pixel electrode layer 106) in order to reduce undesired reflection and color shifts.
Regarding Claim 4, Suzuki further discloses (as shown in Fig. 1) wherein the planarization layer comprises organic photoresist, ([0061] The organic insulating layer 21 is formed of, for example, a photosensitive resin material.)
and the pixel electrode comprises indium tin oxide. ([0064] The pixel electrode 24 is formed of a transparent conductive material (e.g., ITO or IZO))
Regarding Claim 5, Yang fails to teach wherein the second refractive index matching layer comprises silicon oxynitride.
Yang teaches the use of silicon oxynitride as a graded refractive index material. ([0075] If desired, graded index layers may be incorporated into display 14 to reduce the impact of other index of refraction discontinuities. For example, if layers 222 and 228 each include a silicon oxide layer and a silicon nitride layer, a graded index layer such as a silicon oxynitride graded index layer may be sandwiched between each of the silicon-oxide-to-silicon-nitride interfaces (or a subset of these graded index layers may be used). ) However, Yang fails to disclose that this is the graded refractive index material between the planarization layer 230 and the common electrode layer 104’; Yang fails to disclose the graded refractive index material between the planarization layer 230 and the common electrode layer 104’. However, silicon oxynitride has a tunable refractive index range (~1.45-2.0) between the refractive index of the photosensitive resin material (~1.3-1.5) of the planarization layer 230 and the ITO material (~1.85), and Yang teaches that silicon oxynitride can be used between other layers as well. ([0070] Silicon oxynitride graded index layers may also be used to smooth index discontinuities between dielectric layers formed from materials with other indices of refraction) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to also use silicon oxynitride at the interface between the planarization layer 230 and the common electrode layer 104’.
Regarding Claim 6, Yang further discloses (as shown in Figs. 7, 11) wherein the electronic device further comprises:
a third refractive index matching layer ([0078] For example, graded index layer 304 may be interposed between layer 200 and layer 306. Layer 304 may have a continuously varying index or a step-wise varying index) disposed on the substrate ([0077] substrate layer 200); (See Fig. 11, showing graded index layer 304 on the substrate 200)
and a buffer layer ([0078] Layers 306 … may be buffer layers (e.g., inorganic buffer layers)) disposed between the third refractive index matching layer (304) and the driving element, (See Fig. 7, showing the thin film transistor is located on top of base layer 210) (See Fig. 11, showing the buffer layer 306 in base layer 210 and on graded index layer 304)
wherein a refractive index of the third refractive index matching layer (304) is in a range between a refractive index of the substrate (200) and a refractive index of the buffer layer (306). ([0077] Layer 300 may have a graded index of refraction (continuously varied or step-wise varied) or may be a dielectric layer with an index value that lies between the index values of layers 200 and 302.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the first and second buffer layers of Yang with the device of Suzuki based on the teachings of Choi. Choi teaches that the buffer layer 111 reduces penetration of foreign matter from the bottom of the substrate. ([0138] The buffer layer 111 may be disposed on the substrate 100 to reduce or block the penetration of foreign matter, moisture or outside air from the bottom of the substrate 100, and provide a flat surface on the substrate 100.) Therefore, it would have been obvious to include the buffer layers of Yang in Suzuki in order to reduce penetration of foreign matter from the bottom of the substrate.
Regarding Claim 7, Yang further discloses (as shown in Figs. 7, 11) wherein the buffer layer (111) comprises silicon oxide or silicon nitride. ([0138] the buffer layer 111 may include silicon oxide (SiOx) or silicon nitride (SiNx))
Regarding Claim 8, Yang further discloses (as shown in Figs. 7, 11) wherein the electronic device further comprises:
a first buffer layer ([0078] Base layer 210 may include layers 304, 306, 308, and 310. Layers 306 … may be buffer layers (e.g., inorganic buffer layers)) disposed on the substrate ([0077] substrate layer 200); (See Fig. 11)
a third refractive index matching layer (([0079] Graded index layer 308) disposed on the first buffer layer (306); ([0079] Graded index layer 308 may be interposed between layer 306 and layer 310.)
and a second buffer layer ([0078] Base layer 210 may include layers 304, 306, 308, and 310. Layers … 310 may be buffer layers (e.g., inorganic buffer layers)) disposed between the third refractive index matching layer (304) and the driving element, (See Fig. 7, showing the thin film transistor is located on top of base layer 210) (See Fig. 11, showing the buffer layer 310 in base layer 210 and on graded index layer 308)
wherein a refractive index of the third refractive index matching layer (308) is in a range between a refractive index of the first buffer layer (306) and a refractive index of the second buffer layer (310). ([0067] To minimize undesired reflections and color shifts, one or more the dielectric layers of display 14 may be fabricated with continuously varying or stepped indices of refraction. These types of varying index of refraction profiles are sometimes referred to as graded index profiles. When a dielectric layer has a graded index, the dielectric layer may serve as an index matching layer that helps smooth out index of refraction discontinuities in the dielectric layers of display 14. A graded index layer may, for example, be sandwiched between first and second layers with respective first and second different index of refraction values. Portions of the graded index layer adjacent to the first layer may have an index of refraction that is equal to or nearly equal to the first index of refraction value. Portions of the graded index layer adjacent to the second layer may have an index of refraction that is equal or nearly equal to the second index of refraction value. There may be any suitable number of graded index layers in display 14 (e.g., one or more, two or more, three or more, four or more, etc.))
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the first and second buffer layers of Yang with the device of Suzuki based on the teachings of Choi. Choi teaches that the buffer layer 111 reduces penetration of foreign matter from the bottom of the substrate. ([0138] The buffer layer 111 may be disposed on the substrate 100 to reduce or block the penetration of foreign matter, moisture or outside air from the bottom of the substrate 100, and provide a flat surface on the substrate 100.) Therefore, it would have been obvious to include the buffer layers of Yang in Suzuki in order to reduce penetration of foreign matter from the bottom of the substrate.
Regarding Claim 9, Yang further discloses (as shown in Figs. 7, 11) wherein the first buffer layer (306) comprises silicon nitride, and the second buffer layer (310) comprises silicon oxide. ([0078] For example, layer 306 may be a silicon nitride layer having an index of refraction of about 2.0 (or 1.9) and layer 310 may be a silicon oxide layer having an index of refraction of about 1.48.)
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki as applied to claim 1 above, and further in view of Choi et. al (US 2021/0376292 A1).
Regarding Claim 18, Suzuki fails to disclose wherein the electronic device further comprises a third conductive layer disposed on the substrate,
Wherein the third conductive layer forms a light shielding element.
Choi discloses (as shown in Fig. 2) wherein the electronic device further comprises a third conductive layer disposed on the substrate, ([0067] A bottom metal layer BML … In one embodiment, for example, the bottom metal layer BML may be located between the auxiliary thin-film transistor TFT′ and the substrate 100.)
Wherein the third conductive layer forms a light shielding element. ([0067] Such a bottom metal layer BML may block external light from reaching the auxiliary thin-film transistor TFT′.)
Choi teaches that the bottom metal layer blocks external light from reaching the auxiliary thin film transistor. ([0067] Such a bottom metal layer BML may block external light from reaching the auxiliary thin-film transistor TFT′.) therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to include a bottom metal layer in Suzuki to block external light from reaching the thin film transistor.
Regarding Claim 19, Suzuki further discloses (as shown in Fig. 1) wherein the driving element further comprises a semiconductor layer ([0055] Each of the plurality of TFTs 10 includes … an oxide semiconductor layer 13)
Choi further discloses (as shown in Fig. 2) the third conductive layer (BML) at least partially overlaps the semiconductor layer. (See Fig. 2, showing the BML layer overlapping with the semiconductor layer of the auxiliary transistor)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights