DETAILED ACTION
This Office Action is in response to the Application filed on 12/21/2023.
Currently, claims 1-15 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
2. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 14A, 14B, and 14C,
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection(s) to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “isolation insulating structure”. There is insufficient antecedent basis for this limitation in the claim. Therefore, the claim has an indefinite scope. For the purpose of examination, this limitation will be read as: “isolation insulating layer”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being obvious over KANG et al. (US Pub. No. 2025/0048636) in view of HWANG et al. (US Pub. No. 2023/0026774).
Regarding independent claim 1, Kang teaches a semiconductor device (Fig. 2) comprising:
a gate structure (Fig. 2, 130M, ¶ [0027]) including gate lines (Fig. 2, 130L1 + 130L2, ¶ [0033]) and insulating layers (Fig. 2, 120, ¶ [0027]) alternately stacked;
a channel structure (Fig. 2, CH, ¶ [0027]) extending through the gate structure, the channel structure including a channel layer (Fig. 11B, 140, ¶ [0030], the Examiner notes that 140 is unlabeled in Fig. 2) and a channel pad (Fig. 11B, 149, ¶ [0039], the Examiner notes that 149 is unlabeled in Fig. 2) connected to the channel layer (Fig. 11B);
a dummy gate structure (Fig. 2, ¶ [0033] teaches that some gate electrodes 130M can be dummy gate electrodes) including stacked dummy gate lines (Fig. 2, 130L1 + 130L2 corresponding to dummy gate electrodes 130M, ¶ [0033]);
a dummy channel structure (Fig. 2, DH, ¶ [0045]) extending through the dummy gate structure (¶ [0033] teaches that some gate electrodes 130M can be dummy gate electrodes. Kang’s dummy gate electrode can either be adjacent to a channel structure CH or a dummy structure DH in a same manner as the gate electrodes 130M. Therefore, it would be obvious to try by one of ordinary skill in the art to have at least one of Kang’s dummy gate electrodes be adjacent to a dummy structure DH since it has been held that choosing from a finite number of identified, predictable solutions with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007)), the dummy channel structure including a dummy channel layer (¶ [0045] teaches that DH has a same structure as CH and would therefore have a corresponding dummy channel layer 140) and a dummy channel pad connected to the dummy channel layer (¶ [0045] teaches that DH has a same structure as CH and would therefore have a corresponding dummy channel pad 149);
an isolation insulating layer (Fig. 2, MS, ¶ [0054]) disposed between the gate structure and the dummy gate structure (it would be obvious that MS would be in-between at least one dummy gate electrode 130M and a gate electrode 130M).
However, Kang does not explicitly teach a dummy pad disposed on the isolation insulating layer between the gate structure and the dummy gate structure.
However, Hwang is a pertinent art that teaches a dummy pad (Fig. 2, 39d, ¶ [0045]) disposed on the isolation insulating layer (Fig. 2, 21d, ¶ [0045]) between the gate structure and the dummy gate structure (Kang’s isolation insulating structure modified according to the teaching of Hwang would be horizontally in-between Kang’s gate electrode and dummy gate electrodes and would therefore fulfill this limitation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kang’s isolation insulating structure to further comprise a dummy pad according to the teaching of Hwang (Fig. 2) in order to increase storage capacity (Hwang ¶¶ [0003]-[0005]).
Regarding claim 5, Kang modified by Hwang teaches the semiconductor device of claim 1, and Hwang teaches that the channel pad (Fig. 2, 39m, ¶ [0037]), the dummy channel pad (Kang ¶ [0045] teaches that their dummy structure DH has a same structure as channel CH. Therefore, Kang modified by Hwang’s dummy channel pad would have a same structure as their channel pad), and the dummy pad (Hwang Fig. 2, 39d, ¶ [0045]) are disposed at substantially the same level (Hwang’s dummy pad is on a substantially same level as their channel pad 39m (see Fig. 2, ¶ [0037]). Therefore, Kang modified by Hwang’s dummy pad would be on a substantially same level as Kang’s channel pad and dummy channel pad).
Regarding claim 6, Kang modified by Hwang teaches the semiconductor device of claim 1, and Hwang teaches that a height of the dummy pad (Fig. 2, 39d, ¶ [0045]) is greater than a height (Fig. 2, the bottom surfaces of 39d and 39m are curved. Therefore, a maximum height of 39d is greater than a minimum height of 39m) of the channel pad (Fig. 2, 39m, ¶ [0037]) and a height of the dummy channel pad (Kang ¶ [0045] teaches that their dummy structure DH has a same structure as channel CH. Therefore, Kang modified by Hwang’s dummy channel pad would have a same structure as their channel pad), and a width of the dummy pad (Fig. 2, Hwang’s dummy pad is on an entire top surface of their insulating region 21d. Therefore, Kang modified by Hwang’s dummy channel pad would be on a whole surface of Kang’s insulating layer MS. Kang modified by Hwang’s dummy channel pad would have a larger width than their channel pad and dummy channel pad because MS has a greater width than CH and DH) is greater than a width of the channel pad and a width of the dummy channel pad.
Regarding claim 7, Kang modified by Hwang teaches the semiconductor device of claim 1, and Kang teaches that in a memory block (Figs. 1 & 5,), the dummy gate structure (¶ [0033] teaches that some gate electrodes 130M can be dummy gate electrodes. In Figs. 2 & 5, Kang’s dummy gate electrode can only be either in BLK1 or BLK2. Therefore, it would be obvious to try by one of ordinary skill in the art to have at least one of Kang’s dummy gate electrodes be in BLK2 since it has been held that choosing from a finite number of identified, predictable solutions with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007)) is disposed in a block edge region (Fig. 5, BLK2, ¶ [0061]), the gate structure (Fig. 2, 130M, ¶ [0027]) is disposed in a block center region (Fig. 5, BLK1, ¶ [0061]), the isolation insulating layer (Fig. 2, MS, ¶ [0054]) is disposed in a boundary region (Fig. 5, area occupied by MS is a boundary area between BLK1 and BLK2), and the boundary region is disposed between the block edge region and the block center region.
Regarding claim 8, Kang modified by Hwang teaches the semiconductor device of claim 1, and Hwang teaches that the dummy pad (Fig. 2, 39d, ¶ [0045]) includes polysilicon (¶¶ [0039] & [0048] teaches that 39d can include polysilicon).
Claims 2-4 and 9-15 are rejected under 35 U.S.C. 103 as being obvious over KANG et al. (US Pub. No. 2025/0048636) in view of HWANG et al. (US Pub. No. 2023/0026774) and further in view of LEE et al. (US Pub. No. 2020/0286530).
Regarding claim 2, Kang modified by Hwang teaches the semiconductor device of claim 1.
However, Kang modified by Hwang does not explicitly teach that the isolation insulating layer includes stacked horizontal portions and vertical portions extending through the horizontal portions.
However, Lee is a pertinent art that teaches that the isolation insulating layer (Fig. 4A, WLCl, ¶ [0061]) includes stacked horizontal portions (Fig. 4A, portions of WLCl at a same height as 240) and vertical portions (Fig. 4A, vertical portion of WLCl in contact with the left horizontal portions of WLCl and vertical portion of WLCl in contact with the right horizontal portions of WLCl) extending through the horizontal portions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shape of Kang’s layer MS according to the teaching of Lee (Fig. 4A) in order to reduce device size (Lee ¶¶ [0031]-[0032]).
Regarding claim 3, Kang modified by Hwang modified by Lee teaches the semiconductor device of claim 2, and Lee teaches that the horizontal portions (Fig. 4A, portions of WLCl at a same height as 240) are disposed to correspond to the gate lines (Fig. 4A, 240, ¶ [0042]) and the dummy gate lines (Kang ¶ [0033] teaches that some of their gate electrodes 130M can be dummy gate electrodes. Therefore, Kang modified by Lee’s horizontal portions would correspond to a height of both gate electrodes 130L1/130L2 and corresponding dummy gate electrodes at a same height).
Regarding claim 4, Kang modified by Hwang modified by Lee teaches the semiconductor device of claim 2, and Lee teaches that the insulating layers (Fig. 4A, 230, ¶ [0042]) extend between the horizontal portions (Fig. 4A, portions of WLCl at a same height as 240) and between the dummy gate lines (Kang ¶ [0033] teaches that some of their gate electrodes 130M can be dummy gate electrodes. Therefore, Kang modified by Lee’s horizontal portions would correspond to a height of both gate electrodes 130L1/130L2 and corresponding dummy gate electrodes at a same height).
Regarding independent claim 9, Kang teaches a semiconductor device (Fig. 2) comprising:
a gate structure (Fig. 2, 130M, ¶ [0027]) including gate lines (Fig. 2, 130L1 + 130L2, ¶ [0033]) and insulating layers (Fig. 2, 120, ¶ [0027]) alternately stacked;
a dummy gate structure (¶ [0033] teaches that some gate electrodes 130M can be dummy gate electrodes. Kang’s dummy gate electrode can either be adjacent to a channel structure CH or a dummy structure DH in a same manner as the gate electrodes 130M. Therefore, it would be obvious to try by one of ordinary skill in the art to have at least one of Kang’s dummy gate electrodes be adjacent to a dummy structure DH since it has been held that choosing from a finite number of identified, predictable solutions with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). Therefore, it would be obvious that MS would be in-between at least one dummy gate electrode 130M and a gate electrode 130M) including stacked dummy gate lines;
an isolation insulating structure (Fig. 2, MS, ¶ [0054])disposed between the gate structure and the dummy gate structure (It would be obvious that MS would be in-between at least one dummy gate electrode 130M and a gate electrode 130M).
However, Kang does not explicitly teach that the isolation insulating structure including stacked horizontal portions and vertical portions extending through the horizontal portions; and a dummy pad disposed on the isolation insulating structure between the gate structure and the dummy gate structure.
However, Hwang is a pertinent art that teaches a dummy pad disposed on the isolation insulating structure between the gate structure and the dummy gate structure.
However, Hwang is a pertinent art that teaches a dummy pad (Fig. 2, 39d, ¶ [0045]) disposed on the isolation insulating structure (Fig. 2, 21d, ¶ [0045]) between the gate structure and the dummy gate structure (Kang’s isolation insulating structure modified according to the teaching of Hwang would be horizontally in-between Kang’s gate electrode and dummy gate electrodes and would therefore fulfill this limitation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kang’s isolation insulating structure to further comprise a dummy pad according to the teaching of Hwang (Fig. 2) in order to increase storage capacity (Hwang ¶¶ [0003]-[0005]).
However, Kang modified by Lee does not explicitly teach that the isolation insulating structure including stacked horizontal portions and vertical portions extending through the horizontal portions.
However, Lee is a pertinent art that teaches that the isolation insulating structure (Fig. 4A, WLCl, ¶ [0061]) including stacked horizontal portions (Fig. 4A, portions of WLCl at a same height as 240) and vertical portions (Fig. 4A, vertical portion of WLCl in contact with the left horizontal portions of WLCl and vertical portion of WLCl in contact with the right horizontal portions of WLCl) extending through the horizontal portions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shape of Kang’s layer MS according to the teaching of Lee (Fig. 4A) in order to reduce device size (Lee ¶¶ [0031]-[0032]).
Regarding claim 10, Kang modified by Hwang modified by Lee teaches the semiconductor device of claim 9, and Lee teaches that the horizontal portions (Fig. 4A, portions of WLCl at a same height as 240) are disposed to correspond to the gate lines (Fig. 4A, 240, ¶ [0042]) and the dummy gate lines (Kang ¶ [0033] teaches that some of their gate electrodes 130M can be dummy gate electrodes. Therefore, Kang modified by Lee’s horizontal portions would correspond to a height of both gate electrodes 130L1/130L2 and corresponding dummy gate electrodes at a same height).
Regarding claim 11, Kang modified by Hwang modified by Lee teaches the semiconductor device of claim 9, Lee teaches that the gate structure (Fig. 4A, 230 + 240, ¶ [0042]) includes the gate lines (Fig. 4A, 240, ¶ [0042]) and insulating layers (Fig. 4A, 230, ¶ [0042]) alternately stacked, and wherein the insulating layers extend between the horizontal portions (Fig. 4A, portions of WLCl at a same height as 240) and between the dummy gate lines (Kang ¶ [0033] teaches that some of their gate electrodes 130M can be dummy gate electrodes. Therefore, Kang modified by Lee’s horizontal portions would correspond to a height of both gate electrodes 130L1/130L2 and corresponding dummy gate electrodes at a same height).
Regarding claim 12, Kang modified by Lee teaches the semiconductor device of claim 9, and Kang teaches a channel structure (Fig. 2, CH, ¶ [0027]) extending through the gate structure (Fig. 2, 130M, ¶ [0027]), the channel structure including a channel layer (Fig. 11B, 140, ¶ [0030], the Examiner notes that 140 is unlabeled in Fig. 2) and a channel pad (Fig. 11B, 149, ¶ [0039], the Examiner notes that 149 is unlabeled in Fig. 2) connected to the channel layer; and
a dummy channel structure (Fig. 2, DH, ¶ [0045]) extending through the dummy gate structure (¶ [0033] teaches that some gate electrodes 130M can be dummy gate electrodes. Kang’s dummy gate electrode can either be adjacent to a channel structure CH or a dummy structure DH in a same manner as the gate electrodes 130M. Therefore, it would be obvious to try by one of ordinary skill in the art to have at least one of Kang’s dummy gate electrodes be adjacent to a dummy structure DH since it has been held that choosing from a finite number of identified, predictable solutions with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007)), the dummy channel structure including a dummy channel layer (¶ [0045] teaches that DH has a same structure as CH and would therefore have a corresponding dummy channel layer 140) and a dummy channel pad (¶ [0045] teaches that DH has a same structure as CH and would therefore have a corresponding dummy channel pad 149) connected to the dummy channel layer.
Regarding claim 13, Kang modified by Hwang modified by Lee teaches the semiconductor device of claim 12, and Kang modified by Hwang teaches that channel pad (Fig. 2, 39m, ¶ [0037]), the dummy channel pad (Kang ¶ [0045] teaches that their dummy structure DH has a same structure as channel CH. Therefore, Kang modified by Hwang’s dummy channel pad would have a same structure as their channel pad), and the dummy pad (Hwang Fig. 2, 39d, ¶ [0045]) are disposed at substantially the same level (Hwang’s dummy pad is on a substantially same level as their channel pad 39m (see Fig. 2, ¶ [0037]). Therefore, Kang modified by Hwang’s dummy pad would be on a substantially same level as Kang’s channel pad and dummy channel pad).
Regarding claim 14, Kang modified by Hwang modified by Lee teaches the semiconductor device of claim 12, and Hwang teaches that a height of the dummy pad (Fig. 2, 39d, ¶ [0045]) is greater than a height (Fig. 2, the bottom surfaces of 39d and 39m are curved. Therefore, a maximum height of 39d is greater than a minimum height of 39m) of the channel pad (Fig. 2, 39m, ¶ [0037]) and a height of the dummy channel pad (Kang ¶ [0045] teaches that their dummy structure DH has a same structure as channel CH. Therefore, Kang modified by Hwang’s dummy channel pad would have a same structure as their channel pad), and a width of the dummy pad (Fig. 2, Hwang’s dummy pad is on an entire top surface of their insulating region 21d. Therefore, Kang modified by Hwang’s dummy channel pad would be on a whole surface of Kang’s insulating layer MS. Kang modified by Hwang’s dummy channel pad would have a larger width than their channel pad and dummy channel pad because MS has a greater width than CH and DH) is greater than a width of the channel pad and a width of the dummy channel pad.
Regarding claim 15, Kang modified by Hwang modified by Lee teaches the semiconductor device of claim 9, and Kang modified by Lee teaches that in a memory block (Figs. 1 & 5,), the dummy gate structure (¶ [0033] teaches that some gate electrodes 130M can be dummy gate electrodes. In Figs. 2 & 5, Kang’s dummy gate electrode can only be either in BLK1 or BLK2. Therefore, it would be obvious to try by one of ordinary skill in the art to have at least one of Kang’s dummy gate electrodes be in BLK2 since it has been held that choosing from a finite number of identified, predictable solutions with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007)) is disposed in a block edge region (Fig. 5, BLK2, ¶ [0061]), the gate structure (Fig. 2, 130M, ¶ [0027]) is disposed in a block center region (Fig. 5, BLK1, ¶ [0061]), the isolation insulating layer (Fig. 2, MS, ¶ [0054]) is disposed in a boundary region (Fig. 5, area occupied by MS is a boundary area between BLK1 and BLK2), and the boundary region is disposed between the block edge region and the block center region.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2022/0028881 by Hossain et al discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2011/0065270 by Shim et al discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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