DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/16/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US Patent Appl. Pub. No. 2012/0280351 A1).
[Re claim 1] Liu discloses the semiconductor device, comprising: a substrate (275); an upper layer (210 and 205) disposed over the substrate and comprises an upper electrical pattern (235) and an alignment mark pattern (255) electrically insulated from the upper electrical pattern; and a lower layer (215) disposed between the substrate (275) and the upper layer (210 and 205) and comprising a lower electrical pattern (245) and a dummy pattern (260) electrically insulated from the lower electrical pattern, wherein the alignment mark pattern (255) overlaps the dummy pattern (260) from a top view (see figure 2B and paragraph [0048]-[0054]).
Liu fails to disclose the selection of “the alignment mark pattern has an optical contrast in relation to the dummy pattern, and the optical contrast is substantially equal to or greater than 50”. However, it would have been obvious to one of ordinary skill in the art at the time of the invention because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996)(claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
[Re claim 2] Liu discloses the semiconductor device wherein the upper layer (205 and 210) comprises a clearance area (200b area of layers 205 and 210) surrounding the alignment mark pattern (255), and the upper electrical pattern (235) is disposed outside the clearance area (see figure 2B).
[Re claim 3] Liu discloses the semiconductor device wherein the dummy pattern (260) completely filling the clearance area (200b area of layers 205 and 210) from a top view (see figure 2B).
[Re claim 4] Liu discloses the semiconductor device wherein the upper electrical pattern (235) is spaced apart from the clearance area (200b area of layers 205 and 210) by a gap (gap between 200a and 200b) (see figure 2B).
Liu fails to disclose the selection of “a gap which is substantially equal to or greater than 5μm”. However, it would have been obvious to one of ordinary skill in the art at the time of the invention because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996)(claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claim 5-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14-23 are allowed.
The following is an examiner's statement of reasons for allowance: Claim 14 allowable because of the closest prior art (US Patent Appl. Pub. No. 2012/0280351 A1) discloses the semiconductor device, comprising: a substrate (275); an upper layer (205 and 210) disposed over the substrate and comprising an upper electrical pattern (235) and an alignment mark pattern (255) electrically insulated from the upper electrical pattern; a lower layer (215) disposed between the substrate and the upper layer and comprising a lower electrical pattern (245) and a dummy pad (260) electrically insulated from the lower electrical pattern, wherein the alignment mark pattern overlaps the dummy pad from a top view (see figure 2B and paragraph [0048]-[0054]). However, the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein an interconnect structure disposed between the lower layer and the substrate, wherein a part of the interconnect circuit of the interconnect structure overlaps the dummy pattern from a top view. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 15-23 depend from claim 14 so they are allowable for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/Primary Examiner, Art Unit 2817
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