Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Comment
This is a Supplemental Officer Action to correct an error in the Office Action mailed on June 4, 2026, wherein claims 2-14 were included in Claim Rejections under 35 USC § 102.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, recited “…a radio-frequency input terminal configured to receive a radio-frequency signal (RFIN); a radio-frequency output terminal configured to output an amplified radio-frequency signal (RFOUT); a first amplification stage circuit (110) comprising a first terminal (gate) coupled to the radio-frequency input terminal (RFIN), a second terminal (drain/top terminal) coupled to the radio-frequency output terminal (RFOUT), and a third terminal; a second amplification stage circuit (120) comprising a first terminal (gate) coupled to the radio-frequency input terminal (RFIN), a second terminal (drain/top terminal) coupled to the radio-frequency output terminal (RFOUT), an internal node (NH), and a third terminal coupled to the internal node; and a variable impedance path (130) coupled to the internal node (NH), and comprising a first terminal coupled to the third terminal of the first amplification stage circuit, and a second terminal coupled to the third terminal of the second amplification stage circuit …” Note the highlight part of the claim, they appear to say third terminal is also the second terminal of the first and second amplifier stages, respectively, because the first terminal of the of the variable impedance path (130) is coupled between the drain/top terminal of transistor (230) of the first amplification stage (110) and the RF output terminal (RFOUT) and internal node (NH/second terminal of the variable impedance path (130)) is coupled between the drain/top terminal of transistor (210) of second stage (120) and the RF output terminal (RFOUT), wherein 3rd and 4th limitations of the claim disclose both second terminal (drain/top terminal) of first and second amplification stages are coupled to the RF output terminal (RFOUT). This is unclear since the claimed subject matters do not correspond with the drawings submitted. Therefore, it is suggested the claim(s) and specification need to change, especially how the terminals are called, so that they both correspond with the drawings.
Regarding claim 2, recited “the second amplification stage circuit (120) further comprises a first transistor (210); and the variable impedance path (130) further comprises a second transistor (220) coupled to a first terminal of the first transistor (210)”. This is unclear since the first terminal (gate/control terminal) of the first transistor (210) is coupled to the RF input terminal (RFIN), see claim 1, 4th limitation.
Regarding claim 3, recited “the first amplification stage circuit (110) further comprises a third transistor (230); and the variable impedance path (130) further comprises a second transistor (220) coupled to a first terminal of the third transistor (230)”. This is unclear since the first terminal (gate/control terminal) of the third transistor (230) is coupled to the RF input terminal (RFIN), see claim 1, 3rd limitation.
Regarding claims 4-14 are also rejected due to their dependency on rejected claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LI et al. (20220231648), hereafter called LI.
Regarding claim 1, LI (Fig. 5) discloses a multi-gain LNA comprising: a radio-frequency input terminal configured to receive a radio-frequency signal (RFIN); a radio-frequency output terminal configured to output an amplified radio-frequency signal (RFOUT); a first amplification stage circuit (M1 and M2) comprising a first terminal (gate/control terminal of M1) coupled to the radio-frequency input terminal (RFIN), a second terminal (drain terminal of M1/M2) coupled to the radio-frequency output terminal (RFOUT), and a third terminal (source terminal of M1/S1); a second amplification stage circuit (M’1 and M’2) comprising a first terminal (gate/control terminal of M’1) coupled to the radio-frequency input terminal (RFIN), a second terminal (drain terminal of M’1/M’2) coupled to the radio-frequency output terminal (RFOUT), an internal node (common node connecting S’1, SWS12 and SW’L1) and a third terminal (source terminal of M’1/S’1) coupled to the internal node; and switch (SWS12) operable as a variable impedance path coupled to the internal node, and comprising a first terminal coupled to the third terminal (S1) of the first amplification stage circuit (M1 and M2), and a second terminal coupled to the third terminal (S’1) of the second amplification stage circuit (M’1 and M’2); wherein the variable impedance path has a low impedance when the variable impedance path is enabled, and the variable impedance path has a high impedance and the internal node is a high impedance node when the variable impedance path is disabled. Note, switch (SWS12) can be switched ON/OFF.
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 2-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 15-20, among other subject matters claimed, prior art(s) does not disclose a switch (220) comprising a first terminal coupled to a node between the first transistor (250) and the second transistor (230), and a second terminal coupled to a node between the third transistor (240) and the fourth transistor (210).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Noori (10,938,348) discloses two parallel cascode pairs, wherein amplifying transistors (M11 and M21) are commonly coupled RFIN and RFOUT via respective cascode transistors (M12 and M22), However, Noori does not disclose a switch coupled between the two set of transistors as claimed. Additional references cited disclose claimed invention, but they all lack the switch connected between the two set of transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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