DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office Action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Election/Restrictions
Applicant's election without traverse of Species II: Figure 6 in the reply filed on 03/26/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2022/0285460 A1 to Kim et al. (hereinafter "Kim").
Regarding Claim 10, Kim teaches a sensing panel, comprising: a substrate (Figs. 2-5; Para. 60-140 of Kim; base layer BL); and a pixel array comprising a plurality of pixel circuit units arranged in an array (Figs. 2-5; Para. 60-140 of Kim; plurality of pixels PX1, PX2, PX3, and PX4 and a plurality of photo sensors PHS1 and PHS2 may be disposed in the display area AA of the display panel 100), each of the pixel circuit units comprising: a metal layer disposed above the substrate (Figs. 2-5; Para. 60-140 of Kim; first sensor electrode SEL1 may be made of a metal); a transparent conductive layer disposed above the metal layer (Figs. 2-5; Para. 79-160 of Kim; second sensor electrode SEL2 may be configured as a metal layer such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir or Cr, and/or a transparent conductive layer such as ITO, IZO, ZnO or ITZO); a light-sensing layer disposed between the metal layer and the transparent conductive layer and configured to receive a light (Figs. 2-5; Para. 79-160 of Kim; light receiving layer LRL); an insulating layer disposed between the metal layer and the transparent conductive layer and laterally surrounds the light-sensing layer (Figs. 2-5; Para. 79-160 of Kim; light receiving layer LRL… first sensor electrode SEL1 may be made of a metal… bank layer BK may be an organic insulating layer); a first thin film transistor comprising a source, a drain, and a gate (Figs. 2-5; Para. 79-140 of Kim; third sensor transistor M3); and a second thin film transistor comprising a source, a drain, and a gate (Figs. 2-5; Para. 79-140 of Kim; first sensor transistor M1), wherein a conductive layer is electrically connected to the drain of the first thin film transistor (Figs. 2-5; Para. 79-140 of Kim; first sensor electrode SEL1 may be connected to the second drain electrode 14 through a contact hole).
Kim does not explicitly disclose that the transparent conductive layer is electrically connected to the drain of the first thin film transistor and the gate of the second thin film transistor.
However, Kim teaches that a gate electrode of the first sensor transistor M1 may be connected to the fifth node N5 (or the first electrode (e.g., first sensor electrode) of the light receiving element LRD) and that the third sensor transistor M3 may be connected between the initialization power line IPL and the fifth node N5. A gate electrode of the third sensor transistor M3 may be the first scan line S1 i. In other words, the third sensor transistor M3 may be connected to the initialization power line IPL and the first sensor transistor M1 (Figs. 2-5; Para. 98-100 of Kim). Since, the drain of M3 and the fate of M1 are connected to the same node, it would only require routine skill for a person of ordinary skill in the art to electrically connect the transparent conductive layer to the drain of the first thin film transistor and the gate of the second thin film transistor based on the teachings of Kim. Therefore, one of ordinary skill in the art would have pursued electrically connecting the transparent conductive layer to the drain of the first thin film transistor and the gate of the second thin film transistor with a reasonable expectation of success that would have yielded predictable results and can be accomplished without any undue experimentation so that the manufacturing cost of the display device may be reduced, and the power consumption of the display device may be minimized.
Regarding Claim 11, Kim does not explicitly disclose that the light-sensing layer comprises silicon-rich oxide.
However, designing a light-sensing layer comprising silicon-rich oxide would only require routine skill for a person of ordinary skill in the art based on the teachings of Kim. Therefore, one of ordinary skill in the art would have pursued designing a light-sensing layer that comprises silicon-rich oxide with a reasonable expectation of success that would have yielded predictable results and can be accomplished without any undue experimentation. In addition, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Furthermore, there is no persuasive evidence in Applicant's specification that the afore-mentioned material of the light-sensing layer is of particular significance.
Regarding Claim 12, Kim teaches that the gate of the first thin film transistor is configured to receive a driving signal (Figs. 2-5; Para. 79-140 of Kim; gate electrode of the third sensor transistor M3 may be the first scan line S1 i).
Regarding Claim 13, Kim teaches that the source of the first thin film transistor is configured to receive a system voltage (Figs. 2-5; Para. 79-140 of Kim; third sensor transistor M3 may be connected between the initialization power line IPL and the fifth node N5).
Regarding Claim 14, Kim teaches that the drain of the second thin film transistor is configured to receive a system voltage (Figs. 2-5; Para. 79-140 of Kim; first sensor transistor M1 may generate a sensing current flowing from the second power line PL2).
Regarding Claim 15, Kim teaches a light source module, wherein a side of the transparent conductive layer away from the substrate is a sensing area, and the light source module is configured to emit the light towards the sensing area, so that the light is reflected from an object disposed in the sensing area through the transparent conductive layer to the light-sensing layer (Figs. 2-5; Para. 79-140 of Kim; light emitting element LED).
Regarding Claim 16, Kim teaches that the light source module is disposed on a side of the substrate away from the sensing area (Figs. 2-5; Para. 79-140 of Kim; light emitting element LED).
Regarding Claim 17, Kim teaches that the light-sensing layer and the insulating layer jointly cover the metal layer (Figs. 2-5; Para. 79-140 of Kim; light receiving layer LRL… first sensor electrode SEL1 may be made of a metal… bank layer BK may be an organic insulating layer).
Allowable Subject Matter
Claims 1-9 are allowed.
The following is an Examiner’s statement of reasons for allowance:
Applicant’s claims presented on 03/26/2026 constitute the basis for the reasons of allowance as the current prior art of record, considered individually or in combination, fails to teach or reasonably suggest the claimed features of claim 1 structurally and functionally interconnected with other limitations in the manner as cited in the claim and dependent claims. Examiner notes that the current invention as disclosed in the independent claims is allowed in its entirety. Each and every limitation working together in concert realizes the current claimed invention’s novelty. No single limitation alone accomplishes the allowability of the inventive independent claim(s), rather each and every limitation of the claim(s) and their disclosed relationships are integral.
None of the references, either singularly or in combination, teach or fairly suggest a sensing panel, comprising: a substrate; a first sensor disposed above the substrate, comprising a first metal electrode layer, a light-sensing layer, and a first transparent electrode layer, and configured to receive a light and correspondingly generate a first sensing signal, wherein the light-sensing layer is disposed on the first metal electrode layer, and the first transparent electrode layer is disposed on the light-sensing layer; a second sensor disposed above the substrate, comprising a second metal electrode layer, an insulating layer, and a second transparent electrode layer, and configured to contact an object and generate a second sensing signal based on a capacitance value between the object and the second metal electrode layer, wherein the insulating layer is disposed on the second metal electrode layer, and the second transparent electrode layer is disposed on the insulating layer; and a first switching element and a second switching element, wherein the first metal electrode layer is electrically connected to the second metal electrode layer and further to the first switching element and the second switching element, and the first transparent electrode layer is electrically connected to the second transparent electrode layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABHISHEK SARMA whose telephone number is (571)272-9887. The examiner can normally be reached on Mon - Fri 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABHISHEK SARMA/
Primary Examiner, Art Unit 2621
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