DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The provisional Nonstatutory Double Patenting rejection of Claims 1–20 over co-pending Application No. 18/391,775 is hereby WITHDRAWN in view of the approved Terminal Disclaimer filed in compliance with 37 CFR 1.321.
Finality of the Action
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant’s arguments with respect to Claims 1–20 have been fully considered but are unpersuasive.
Applicant argues that Wang (CN 112436846) fails to teach or suggest an RF module featuring a substrate divided into distinct layout areas where a first RF chip (comprising low and intermediate frequency power amplifiers) and a second RF chip (comprising higher frequency power amplifiers) are routed to respective first and second switch chips.
However, Wang explicitly discloses a highly integrated RF front-end architecture comprising a first transmitting module (handling low-frequency signals) routed to a low-frequency switch circuit, and a second transmitting module (handling intermediate and high-frequency signals) routed to a medium-high frequency switch circuit, all disposed on a common module substrate. To the extent Wang does not explicitly label these physical regions as "first layout area" and "second layout area," it is well settled that physical grouping and spatial separation of high-frequency and low-frequency components on a substrate to optimize routing and avoid electromagnetic interference is a matter of conventional engineering practice and design choice to a Person Having Ordinary Skill in The Art (PHOSITA). Please see attached the original Chinese patent document of Wang and brief description of the invention along with Figures and the reference of layout related topics summarized in Standard English from the page and paragraph numbers of the original Chinese document attached as a foreign reference.
Regarding the minor amendments to Claims 1, 5, 10, 11, and 18:
Claim 1 & 18: The clarification of the first and second layout areas and signal output routing merely formalizes the expected physical layout and basic functional connection of the power amplifiers to their corresponding switches as already rendered obvious by CN 112436846.
Claims 5, 10, and 11: The structural limitations regarding switch units, power supply ports, and balun trace configurations (primary-side and secondary-side trace parts surrounding capacitors) represent conventional RF matching and balun layout techniques predictable in the art to achieve impedance matching and common-mode noise suppression.
Accordingly, the prior art of record establishes a prima facie case of obviousness, and the amendments fail to distinguish the claimed subject matter over the combined teachings.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness Rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (CN112436846, published on March 15, 2022) in view of Chang et al. (US 2026/0019095 A1, effectively filing date Dec. 26, 2019).
Overall, in the rejection, Wang discloses an RF front-end module architecture featuring a substrate with multiple layout areas housing first and second RF chips. Crucially, it teaches the segregation of signal paths by frequency and the physical arrangement of switch chips to handle outputs from multiple power amplifiers.
While Chang is utilized to address specific circuit-level limitations in the dependent claims. It provides detailed implementations of impedance matching components, including parallel capacitor configurations, on-substrate winding inductors, and specialized balun structures with primary/secondary trace parts for signal coupling.
Key Mappings & Rationale
Claim Element
Prior Art Mapping / Rationale
Module Architecture (Cl. 1, 17)
Wang: Shows substrate layout with multi-amplifier chips and switch chips.
Frequency Hierarchy (Cl. 2)
Wang: Describes segregating high/low bands (N77/N79 vs. MB/LB).
Matching Circuits (Cl. 3-6, 12-13)
Chang: Details baluns and parallel capacitors for impedance tuning.
Control & Routing (Cl. 10-11, 16)
Wang: Integrates logic/control chips and bridge/jumper routing.
Substrate Design (Cl. 14-15)
Wang & Chang: Teach 2-layer stacks and integrated winding inductors.
Legal Rationale for Combination:
A Person Having Ordinary Skill In The Art (PHOSITA) would be motivated to combine the system-level architecture of Wang with the component-level optimizations of Chang to achieve predictable improvements in signal integrity, miniaturization, and frequency-specific tuning in high-performance RF modules.
Regarding Claims 1 and 18, Wang teaches:
An RF module, comprising:
a substrate, the substrate comprises a first layout area and a second layout area, wherein the first layout area and the second layout area are located at different parts of the substrate respectively; and the substrate is also provided with a first signal output port and a second signal output port (Figs. 1–3, Section [0022]–[0028] disclosing a multi-layer RF substrate divided into distinct layout regions for handling different frequency bands, provided with multiple signal output ports);
a first RF chip, the first RF chip is arranged in the first layout area and comprises a first power amplifier and a second power amplifier, the first power amplifier is configured to receive a first input signal, the second power amplifier is configured to receive a second input signal, and a frequency of the first input signal is lower than that of the second input signal (Figs. 1–2, Section [0030]–[0035] disclosing a low/mid-band RF IC placed in the first layout region containing a first power amplifier for a low-frequency signal f1 and a second power amplifier for a mid-frequency signal f2, where f1 < f2);
a first switch chip, the first switch chip is arranged in the first layout area and connected to an output end of the first power amplifier and an output end of the second power amplifier respectively; the first switch chip is further respectively connected to the first signal output port and the second signal output port: wherein the first signal output port is configured to output the first input signal after power amplification by the first power amplifier, and the second signal output port is configured to output the second input signal after power amplification by the second power amplifier (Figs. 1–3, Section [0038]–[0042] disclosing a switch IC in the first layout area connected to outputs of the PAs and routing the amplified low- and mid-frequency signals to respective output ports);
a second RF chip, the second RF chip is arranged in the second layout area and comprises a third power amplifier, the third power amplifier is configured to receive a third input signal, and a frequency of the third input signal is higher than that of the second input signal (Figs. 1–2, Section [0045]–[0048] disclosing a high-band RF IC located in the second layout area containing a third power amplifier receiving a high-frequency signal f3, where f3 > f2); and
a second switch chip, the second switch chip is arranged in the second layout area and connected to an output end of the third power amplifier (Figs. 1–3, Section [0050]–[0052] disclosing a second switch IC arranged in the second layout area connected to the output of the third power amplifier).
Wang, however, does not explicitly disclose that the output ports on the substrate are arranged such that a distance between the first signal output port (low-frequency) and the second signal output port (mid-frequency) is smaller than a distance between the first signal output port (low-frequency) and a third signal output port associated with the higher-frequency path of the second layout area.
In the same field of endeavor (RF module substrate layout and parasitic minimization), Chang et al. teach arranging substrate output ports according to frequency band adjacency to reduce routing parasitic capacitance and minimize signal crosstalk (Figs. 3A–4B; Paragraphs [0034]–[0042], [0055]–[0060]). Specifically, Chang et al. disclose placing ports for adjacent lower frequency bands (e.g., low-band and mid-band) closer to one another while spacing ports for non-adjacent or higher frequency bands (e.g., high-band) further apart (Paragraphs [0038]–[0041]), thereby explicitly teaching that the physical distance between first (low-band) and second (mid-band) signal output ports is smaller than the physical distance between first (low-band) and third (high-band) signal output ports.
It would have been obvious to a person having ordinary skill in the art (POSITA) before the effective filing date of the claimed invention to modify the substrate port arrangement of Wang to configure the physical relative distances between the signal output ports associated with the respective frequency paths such that the distance between the first and second output ports is smaller than the distance between the first and third output ports, as taught by Chang et al.
The motivation for incorporating Chang et al.'s relative port spacing arrangement into Wang's dual-layout RF module substrate is to optimize trace routing density and significantly reduce electromagnetic coupling and crosstalk between non-adjacent frequency paths. As taught by Chang et al., placing adjacent lower-frequency band ports closer together streamlines trace layout on the substrate, while increasing the physical distance to the highest-frequency band port prevents high-frequency harmonic interference and capacitive isolation loss. Applying this spatial arrangement to Wang's dual-layout RF module yields the predictable result of preserving signal integrity across high-frequency paths while maintaining compact substrate area.
The modified combination of Wang in view of Chang et al. thereby teaches all limitations of claims 1 and 18.
Claim 2: Power Amplifier Frequencies
Limitation: Freq(PA3) > Freq(PA2) > Freq(PA1).
Mapping: Wang teaches segregating chips by frequency bands, where the third path is specifically for high-frequency (e.g., N77/N79) while others handle lower bands (e.g., LB/MB).
Rejection: Obvious over Wang.
Claim 3 & 4: Matching Module & Capacitors
Limitation: Matching module between PA and switch; contains parallel capacitors.
Mapping: Chang (Fig. 4, ref C1, C2) discloses matching circuits with parallel capacitor banks used to tune impedance.
Rejection: Obvious over Wang in view of Chang.
Claim 5 & 6: Balun and Trace Structures
Limitation: Third matching module comprises a balun with primary and secondary trace parts.
Mapping: US Chang (Fig. 6, ref 601, 602) explicitly details a balun structure for RF matching, showing the primary and secondary coupling areas.
Rejection: Obvious over Wang in view of Chang
Claim 7: Substrate Material
Limitation: Substrate composed of two metal layers.
Mapping: This is a standard manufacturing choice in RF modules to reduce thickness and cost, as taught in Wang.
Rejection: Obvious over Wang.
Claim 8: First and Second Matching Modules
Limitation: Includes a first and second matching module; first matching module is between the first RF chip and first switch chip.
Mapping: Wang (Fig. 1) illustrates matching networks (ref 50, 60) positioned directly between the output of the RF amplifier chips and the input of the switch chips to ensure power transfer.
Rejection: Obvious over Wang.
Claim 9: Signal Pin Placement
Limitation: First signal pin arranged on a third side of the first RF chip adjacent to the first matching module.
Mapping: Wang teaches optimized chip layouts where output pins are positioned on the side closest to the matching components to minimize trace length and parasitic inductance.
Rejection: Obvious over Wang.
Claim 10: Control Chip Arrangement
Limitation: Module further comprising a control chip; first RF chip, control chip, and second RF chip are sequentially arranged.
Mapping: Wang (Fig. 2) shows a controller or logic chip (ref 70) integrated on the substrate alongside the RF chips to manage switching states. Sequential arrangement is a standard layout choice for space efficiency.
Rejection: Obvious over Wang.
Claims 11: Switch Unit and Control Unit
Limitation: Control chip includes a switch unit and control unit for switching sub-bands.
Mapping: US Chang (Fig. 3) describes a control logic unit that interfaces with a switch unit to select specific frequency sub-paths based on the required band (e.g., N77 vs N79).
Rejection: Obvious over Wang in view of US Chang.
Claims 12-13: Matching Module Components (Balun)
Limitation: Third matching module comprises a first balun with coupled coils forming first and second coupling areas.
Mapping: US Chang (Fig. 6) details a balun structure (ref 601, 602) where interleaved coils create specific coupling areas for differential-to-single-ended conversion.
Rejection: Obvious over Wang in view of US Chang.
Claim 14: Metal Layers
Limitation: Substrate composed of two metal layers.
Mapping: Wang discloses the use of multi-layer laminate or PCB substrates, where reducing the stack to two layers is a known cost-saving and thinning technique.
Rejection: Obvious over Wang.
Claim 15: Matching Inductor
Limitation: Substrate provided with a matching inductor formed through metal winding on the same layer.
Mapping: US Chang (Fig. 5) shows on-substrate spiral inductors (ref L1) used for matching, fabricated using standard metal traces on the substrate surface.
Rejection: Obvious over Wang in view of US Chang.
Claim 16: Bridge Module/Jumper Wire
Limitation: Control chip connected to the second switch chip through a bridge module (first trace and jumper wires).
Mapping: Wang discusses the use of routing traces and bonding wires (jumpers) to connect logic signals from a central controller to peripheral switch chips when crossing other signal paths.
Rejection: Obvious over Wang.
Claims 17, 19-20: Independent RF Module (Alternative Embodiment)
Limitation: Features an RF module with specific matching modules (2nd and 3rd) arranged along intersecting directions.
Mapping: Wang (Fig. 1, 4) shows the second and third signal paths oriented at 90-degree angles (intersecting directions) to maximize physical isolation and reduce electromagnetic interference (EMI) between high-power outputs. The placement of signal output ends (M, N, K) on different sides of the substrate is explicitly taught.
Rejection: Obvious over Wang.
Summary of the Combination Rationale
The combination is based on the rationale that a PHOSITA would look to Chang to find specific circuit-level implementations (baluns, parallel capacitors, and winding inductors) to fulfill the performance requirements of the module architecture disclosed in Wang. The results are predictable improvements in signal tuning and module miniaturization.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights