DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites “standard operating modes “ . It is unclear what “standard” mode of a capacitor is . For examination purpose the discharging mode is considered as standard mode. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 9, 14-19 and 22-23 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yang et al. (US 2018/0079315), hereinafter Yang.
As to claim 1, 16 and 22, Yang discloses in figures 18 and 10, a circuit comprising [see figure 8-reporudced below]
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: a first power transistor [first transistor (61)] comprising a first gate terminal [gate driver (63)] ; and
a second power transistor [second transistor (62)] comprising a second gate terminal [gate driver (64)] , the second power transistor connected in series with the first power transistor, wherein a capacitor [capacitor 16; see figure 10] , the first power transistor, and the second power transistor are located on a discharge current pathway [Dc link charger line (14)] ; and
a controller [controller (68) and also figure 10] configured to: control the first power transistor to perform a sequence of first switching cycles by applying, for each switching cycle of the sequence of first switching cycles, a first gate voltage to the first gate terminal, the first gate voltage exceeding a threshold gate voltage so that the first power transistor operates according to a non-linear transfer function [noted during the first charging cycle the gate driver applies gate voltage in charging pulse sequences to turn on the transistor switch (61) to discharge the capacitor (16); see Abstract and ¶0033-0034];
control the second power transistor [transistor (62)] to perform a sequence of second switching cycles by applying, for each switching cycle of the sequence of second switching cycles, a second gate voltage to the second gate terminal, the second gate voltage exceeding the threshold gate voltage so that the second power transistor operates according to the non-linear transfer function; and by controlling the first power transistor to perform the sequence of first switching cycles and controlling the second power transistor to perform the sequence of second switching cycles, cause the capacitor to discharge according to a sequence of discharge phases via the discharge current pathway[noted during the first charging cycle the gate driver applies gate voltage in charging pulse sequences to turn on the transistor switch (62) to discharge the capacitor (16); and ¶0033-0034; noted that during on time both switching device is in the ON state and the other switching device is in the OFF state];.
Regarding Claim 22, Yang discloses the claim limitations as claim 1 above and further, a capacitor [16] is disclosed[ see figures 8 and 10]
As to claims 2 and 17. Yang discloses in figures 8 and 10, wherein to cause the capacitor to discharge according to the sequence of discharge phases, the controller is configured to cause, for each discharge phase of the sequence of discharge phases, electrical current to flow from the capacitor via the discharge current pathway [pulse trains are disclosed to turn on and off of the transistor switches; see ¶0030-0034].
As to claims 3 and 18, Yang discloses in figures 8 and 10, wherein to cause the capacitor to discharge according to the sequence of discharge phases, the controller is configured to cause a voltage of the capacitor to discharge from a first voltage value to a second voltage value, each discharge phase of the sequence of discharge phases decreasing the voltage of the capacitor until the voltage of the capacitor is equal to the second voltage value [the capacitor is discharged form a first (or higher voltage) to a lover voltage threshold (second voltage) such as 60V or low voltage level; see ¶0005, ¶0006 and ¶0023].
As to claims 5 and 19, Yang discloses in figures 1-10, wherein to cause the capacitor to discharge according to the sequence of discharge phases [train pulses are controlling the discharging of the capacitor] , the controller is configured to, for each discharge phase of the sequence of discharge phases: cause electrical current to flow from the capacitor across the first power transistor and the second power transistor in response to both of the first power transistor and the second power transistor being activated; and prevent electrical current from flowing from the capacitor across the first power transistor and the second power transistor in response to one or both of the first power transistor and the second power transistor being deactivated [as shown in figures 8-10; during discharging the capacitor discharges to the load ; see ¶0033-0034].
/As to claim 6, Yang discloses in figures 1-10, wherein to cause the capacitor to discharge according to the sequence of discharge phases, the controller is configured to, for each discharge phase of the sequence of discharge phases: cause electrical current to flow from the capacitor across the first power transistor and the second power transistor in response to both of the first power transistor and the second power transistor being activated; and prevent electrical current from flowing from the capacitor across the first power transistor and the second power transistor in response to one or both of the first power transistor and the second power transistor being deactivated [noted during the first charging cycle the gate driver applies gate voltage in charging pulse sequences to turn on the transistor switch (61) to discharge the capacitor (16); the second charging cycle the gate driver applies gate voltage in charging pulse sequences to turn on the transistor switch (62) to discharge the capacitor (16); and ¶0033-0034; noted that during on time both switching device is in the ON state and the other switching device is in the OFF stat; the discharge current flows via DC link bus to the moto ; see also ¶0031-0034r];.
As to claim 9, Yang discloses inf figures 7-9, wherein each first switching cycle of the sequence of first switching cycles comprises a first activation phase and a first deactivation phase [see figure 8; ¶0031-0034], wherein each second switching cycle of the sequence of second switching cycles comprises a second activation phase [see figure 8, different phase signals with different phases are disclosed to control the transistors ] and a second deactivation phase, and wherein each discharge phase of the sequence of discharge phases corresponds to a combination of a first activation phase of a first switching cycle of the sequence of first switching cycles and a second activation phase of a second switching cycle of the sequence of second switching cycles [in combination of the transistors switch the capacitor discharges via the DC link bus to the motor].
. As to Claim 14, yang discloses in figures 7-10, wherein the controller is configured to: identify one or more standard operating modes prompting a discharge operation to cause the capacitor to discharge; and initiate the discharge operation based on identifying the one or more standard operating modes, wherein the discharge operation includes the first power transistor performing the sequence of first switching cycles and the second power transistor performing the sequence of second switching cycles [during discharging mode the capacitor is considered in standard mode and discharges the battery based on the gate control voltage]..
+As to claim 15, Yang discloses in figures 1-10, wherein the capacitor comprises a direct current (DC) link capacitor connected to an inverter circuit for an electrical motor of a vehicle [see Abstract].
As to claim 23, Yang discloses in figures 1-10, a first gate driver circuit [first gate driver (63)] ; and a second gate driver circuit [second gate driver (64)] , wherein to control the first power transistor to perform the sequence of first switching cycles, the controller is configured to output a first control signal to the first gate driver circuit to cause the first gate driver circuit to perform the sequence of first switching cycles, and wherein to control the second power transistor to perform the sequence of second switching cycles, the controller is configured to output a second control signal to the second gate driver circuit to cause the second gate driver circuit to perform the sequence of second switching cycles [see ¶0031=0034]..
Noted that the method merely recites the steps of using the elements of the device as disclosed above. Thus, the method steps will be met during the normal operation of the apparatus described above.
. Allowable Subject Matter
Claims 4, 7-8, 10-13 and 20-21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For Claim 4: primarily, the prior art of record does not disclose or suggest in the claimed combination: a voltage sensor configured to generate a voltage signal indicating the voltage of the capacitor, and wherein the controller or safety logic is configured to: determine, based on the voltage signal, that the voltage of the capacitor is equal to the second voltage value; control the first power transistor to cease the sequence of first switching cycles based on determining that the voltage of the capacitor is equal to the second voltage value; and control the second power transistor to cease the sequence of second switching cycles based on determining that the voltage of the capacitor is equal to the second voltage value.
For Claim 7: primarily, the prior art of record does not disclose or suggest in the claimed combination: wherein to cause the capacitor to discharge according to the sequence of discharge phases, the controller is configured to, for each discharge phase of the sequence of discharge phases: cause electrical current from the capacitor to charge a parasitic capacitance of the first power transistor; cause the parasitic capacitance of the first power transistor to discharge to charge a parasitic capacitance of the second power transistor; and cause the parasitic capacitance of the second power transistor to discharge.
For Claim 10_:primarily, the prior art of record does not disclose or suggest in the claimed combination: wherein the sequence of first switching cycles includes a first plurality of short activation phases and a first plurality of long activation phases interleaved with the first plurality of short activation phases, wherein a duration of each short activation phase of the first plurality of short activation phases is shorter than a duration of each long activation phase of the first plurality of long activation phases, wherein the sequence of second switching cycles includes a second plurality of short activation phases and a second plurality of long activation phases interleaved with the second plurality of short activation phases, wherein a duration of each short activation phase of the second plurality of short activation phases is shorter than a duration of each long activation phase of the second plurality of long activation phases, and wherein each discharge phase of the sequence of discharge phases corresponds to: a period of overlap between a short activation phase of the first plurality of short activation phases and a long activation phase of the second plurality of long activation phases; or a period of overlap between a short activation phase of the second plurality of short activation phases and a long activation phase of the first plurality of long activation phases.
For Claim 11: primarily, the prior art of record does not disclose or suggest in the claimed combination: wherein each discharge phase of the sequence of discharge phases corresponds to: a period of time following a start of an activation phase of the first plurality of activation phases; or a period of time following a start of an activation phase of the second plurality of activation phases.
For Claim 12: primarily, the prior art of record does not disclose or suggest in the claimed combination: wherein the sequence of first switching cycles includes a first plurality of activation phases, each activation phase of the first plurality of activation phases ending in a first soft turn off phase where the first gate voltage decreases over the first soft turn off phase, wherein the sequence of second switching cycles includes a second plurality of activation phases, each activation phase of the second plurality of activation phases ending in a second soft turn off phase where the second gate voltage decreases over the second soft turn off phase, and wherein each discharge phase of the sequence of discharge phases corresponds to: a period of overlap between the first soft turn off phase of an activation phase of the first plurality of activation phases and an activation phase of the second plurality of activation phases; or a period of overlap between the second soft turn off phase of an activation phase of the second plurality of activation phases and tan activation phase of the first plurality of activation phases.
For Claim 13 :Primarily, the prior art of record does not disclose or suggest in the claimed combination: wherein the controller is configured to: identify one or more failure conditions prompting a discharge operation to cause the capacitor to discharge; and initiate the discharge operation based on identifying the one or more failure conditions, wherein the discharge operation includes the first power transistor performing the sequence of first switching cycles and the second power transistor performing the sequence of second switching cycles.
wherein the controller is configured to: identify one or more failure conditions prompting a discharge operation to cause the capacitor to discharge; and initiate the discharge operation based on identifying the one or more failure conditions, wherein the discharge operation includes the first power transistor performing the sequence of first switching cycles and the second power transistor performing the sequence of second switching cycles.
For Claim 20: primarily, the prior art of record does not disclose or suggest in the claimed combination: wherein causing the capacitor to discharge according to the sequence of discharge phases comprises, for each discharge phase of the sequence of discharge phases: causing, by the controller, electrical current from the capacitor to charge a parasitic capacitance of the first power transistor; causing, by the controller, the parasitic capacitance of the first power transistor to discharge to charge a parasitic capacitance of the second power transistor; and causing, by the controller, the parasitic capacitance of the second power transistor to discharge.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (US 2020/0067400) discloses Gate driver controller and associated discharge method.
Sakai et al. (US 2012/0385206) inverter device
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/SAMUEL BERHANU/Primary Examiner, Art Unit 2859
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