Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, 17 recite “a first gate material and a second gate material” however the specification does not describe what this mean, see PG-PUB paragraph 0026, 0031, 0035, 0042 “Gate material 110 (and material 111) may be flanked” “Gate material 210 and material 211 may be electrically isolated from each other” “gate material of gate region 210 may comprise one or more of polysilicon, tungsten, titanium nitride (TiN) and/or any other suitable metal” “In a next step c) a liner oxide layer may be deposited that covers an inside of the one or more trenches. Next, in step d), a gate material (e.g. polysilicon) may be provided, e.g. by deposition, in each of the one or more trenches”. Thus it is assumed that the gate material may include two portions such as 210, 211 or it can include only a gate of polysilicon with metal contact.
Claim 17 recites “wherein the gate region comprises a first gate material and a second gate material” and “etching a recess along a portion of a vertical dimension of the vertical gate region and the oxide region” however see PG-PUB paragraph 0039-0042 “In step 502, a vertical transistor manufacturing intermediate having a trench gate region and oxide region may be provided. A recess may be etched 504 along a portion of the vertical dimension of the trench gate and oxide regions” “A further material 211 may be added to the recess, connected to a source electrode” and “In a next step c) a liner oxide layer may be deposited that covers an inside of the one or more trenches. Next, in step d), a gate material (e.g. polysilicon) may be provided, e.g. by deposition, in each of the one or more trenches”, thus in the specification the polysilicon is deposited at the end. The Examiner notes that the figures provided do not show the fabrication sequence, thus even the specification description is not clear as to what the invention fabrication steps are. Thus it is assumed that in claim 17 the “wherein the gate region comprises a first gate material and a second gate material” occurs at the end of the gate formation and similarly that the oxide region of claim 17 can be the gate insulation region formed just prior to forming the gate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsujimura et al. (US 20180240906 A1) hereafter referred to as Tsujimura in view of Kim et al. (US 20200212218 A1) hereafter referred to as Kim
In regard to claim 1 Tsujimura teaches a [see Fig. 1, Fig. 2, Fig. 3, Figs. 6-17 see paragraph 0031 “A switching element 10 of an embodiment shown in FIGS. 1 to 3 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)” “FIG. 6 shows an explanatory diagram of a manufacturing method of the embodiment”] trench transistor, comprising:
a gate region [“Each of the trenches 22 has a gate electrode 26 arranged therein”] comprising a gate material;
an gate insulating layer region [“As shown in FIGS. 2 and 3, an inner surface of each of the trenches 22 is covered by a gate insulating layer 24. Each gate insulating layer 24 includes a bottom insulating layer 24a and a lateral insulating layer 24b”] adjacent to the gate region;
a semiconductor region [“As shown in FIGS. 1 to 3, a plurality of source regions 30, a plurality of body contact regions 31, a plurality of body regions 32, a drift region 33, a drain region 34, a plurality of bottom p-type regions 36, and a plurality of connecting p-type regions 38 are provided inside the semiconductor substrate 12”] adjacent to the gate insulating layer region;
wherein the semiconductor region comprises a channel body [“body regions 32”] region along a gate- oxide-semiconductor boundary, wherein the channel body region is configured to conduct current [“When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] along the gate-oxide-semiconductor boundary when the transistor is turned on; and
wherein the gate-oxide-semiconductor boundary [see top view in Fig. 1, see Fig. 2, Fig. 3, see “As shown in FIGS. 2 and 3, the body region 32 is distributed over both the wide portions 20a and the narrow portions 20b” i.e. see the shape in top view of lateral insulating layers 24b, see wide and narrow regions ] has a nonlinear shape
but does not state that the gate material is a first gate material and a second gate material and that the gate insulating layer is oxide region.
However see that in the term Metal-Oxide-Semiconductor Field-Effect Transistor, the insulator is is called Oxide because that is the most common gate insulator in a FET.
See Kim teaches see Fig. 2 “an active area 210, with a plurality of active trench gates 105 having a double shield field plate 105b, 105c in the active area 210” “active trench gates 105 each have a polysilicon gate 105a with a gate dielectric layer 105d having a horizontal portion below the polysilicon gate 105a and having a vertical portion between the sidewalls of the polysilicon gate 105a and the pbody region 102 and the source region 103. The double shield field plate 105b, 105c is shown below the gate dielectric layer 105d under the polysilicon gate 105a. The gate dielectric layer 105d when it comprises thermal silicon oxide may be thicker in the horizontal portion above the double shield field plate 105b, 105c (due to a higher thermal oxidation rate for polysilicon relative to single crystal silicon) as compared to its thickness on the vertical portion of the trench sidewall of the pbody region 102 and the source region 103” “a metal contact 118b connecting together the polysilicon gates 105a of the active trench gates 105”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify that the gate material is a first gate material and a second gate material and that the gate insulating layer is oxide region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that thermal silicon oxide is known to give excellent results as gate dielectric and polysilicon gate with metal gate contact and a field plate gives good gate control of channel, with good gate conduction and good field control inside the device.
In regard to claim 2 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 see there are alternately wide and narrow portions i.e. a piecewise linear shape] wherein the nonlinear shape comprises a piecewise linear shape.
In regard to claim 3 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the trench gate] wherein the oxide region is immediately adjacent to the gate region.
In regard to claim 4 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the semiconductor region is immediately adjacent to the oxide region.
In regard to claim 5 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the trench transistor is a trench gate power metal-oxide-semiconductor field effect transistor.
In regard to claim 6 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 “Firstly, as shown in FIG. 6, the drift region 33, the body region 32, the source region 30, and the body contact regions 31 are formed on the drain region 34 by epitaxial growth, ion implantation, and the like”] wherein the semiconductor region is an epitaxial region.
In regard to claim 7 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the trench transistor is a trench vertical transistor.
In regard to claim 8 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 see there are alternately wide and narrow portions i.e. a periodic rectangular shape] wherein the piecewise linear shape is a periodic rectangular shape.
In regard to claim 9 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the oxide region is immediately adjacent to the gate region.
In regard to claim 10 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the semiconductor region is immediately adjacent to the oxide region.
In regard to claim 11 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the trench transistor is a trench gate power metal-oxide-semiconductor field effect transistor.
In regard to claim 12 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 “Firstly, as shown in FIG. 6, the drift region 33, the body region 32, the source region 30, and the body contact regions 31 are formed on the drain region 34 by epitaxial growth, ion implantation, and the like”] wherein the semiconductor region is an epitaxial region.
In regard to claim 13 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the trench transistor is a trench vertical transistor.
In regard to claim 14 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the oxide region is immediately adjacent to the gate region.
In regard to claim 15 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the semiconductor region is immediately adjacent to the oxide region.
In regard to claim 16 Tsujimura and Kim as combined teaches [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] wherein the trench transistor is a trench gate power metal-oxide-semiconductor field effect transistor.
Claim(s) 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsujimura et al. (US 20180240906 A1) hereafter referred to as Tsujimura in view of Kim et al. (US 20200212218 A1) hereafter referred to as Kim
In regard to claim 17 Tsujimura teaches a [see Fig. 1, Fig. 2, Fig. 3, Figs. 6-17 see paragraph 0031 “A switching element 10 of an embodiment shown in FIGS. 1 to 3 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)” “FIG. 6 shows an explanatory diagram of a manufacturing method of the embodiment”] a method of manufacture of a nonlinear vertical transistor gate, comprising the steps of:
providing a vertical transistor manufacturing intermediate having a vertical gate region [see Fig. 7 see that the gate region is the trenches between mask 200 “as shown in FIG. 7, a mask 200 having openings 200a is formed on the upper surface 12a of the semiconductor substrate 12 to etch the upper surface 12a within the openings 200a”] and an masking region;
etching a recess along a portion of a vertical dimension [see Fig. 7 “etch the upper surface 12a within the openings 200a”] of the vertical gate region and the masking region;
depositing [“Next, as shown in FIG. 9, a mask 210 covering a surface of the mask 200 and insides of the trenches 22 is formed”] a photoresist layer;
developing a mask in the photoresist layer so that the mask covers [“Next, as shown in FIG. 10, the mask 210 inside the trenches 22 in the second range 112 is removed by etching. An entirety of the first range 111 is maintained in the state of being covered by the mask 210. Further, an upper surface of the mask 200 in the second range 112 is also maintained in the state of being covered by the mask 210”] a first portion of the recess and exposes a second portion of the recess; and
isotropically etching [“Next, as shown in FIG. 11, the inner surfaces of the trenches 22 in the second range 112 are etched by isotropic etching. Due to this, the connecting p-type regions 38 in the second range 112 are removed. Further, as a result of this, the width of the trenches 22 in the second range 112 is enlarged. As a result, the narrow portions 20b at each of which the interval between the trenches 22 is narrow are formed in the second range 112. Since the semiconductor substrate 12 in the first range 111 is covered by the mask 210, it is not etched at this stage. Due to this, the intervals between the trenches 22 are wider in the first range 111 than in the second range 112. That is, a region between each pair of the trenches 22 in the first range 111 becomes the wide portion 20a. As a result, as shown in FIG. 1, the structure in which the wide portions 20a and the narrow portions 20b are arranged alternately along the y direction between each pair of trenches 22 is formed”] the exposed second portion of the recess, while the first portion of the recess is protected, thereby providing a nonlinear shape for providing the nonlinear vertical transistor gate,
then see gate formation “Then, as shown in FIG. 15, the protective oxide film 220 is removed, and the gate insulating layers 24 and the gate electrodes 26 are formed in the trenches 22”.
but does not state that the masking region is oxide region and that “wherein the gate region comprises a first gate material and a second gate material”.
However see the 112 rejection above, see PG-PUB paragraph 0039-0042 “In step 502, a vertical transistor manufacturing intermediate having a trench gate region and oxide region may be provided. A recess may be etched 504 along a portion of the vertical dimension of the trench gate and oxide regions” “A further material 211 may be added to the recess, connected to a source electrode” and “In a next step c) a liner oxide layer may be deposited that covers an inside of the one or more trenches. Next, in step d), a gate material (e.g. polysilicon) may be provided, e.g. by deposition, in each of the one or more trenches”, thus in the specification the polysilicon is deposited at the end. Thus it is assumed that in claim 17 the “wherein the gate region comprises a first gate material and a second gate material” occurs at the end of the gate formation and similarly that the oxide region of claim 17 can be the gate insulation region formed just prior to forming the gate.
See paragraph 0060 use of oxide as a mask “a protective oxide film 220 is grown” “the bottom p-type regions 36 are formed by implanting” “the protective oxide film 220 is removed”.
However see that in the term Metal-Oxide-Semiconductor Field-Effect Transistor, the insulator is is called Oxide because that is the most common gate insulator in a FET.
See Kim teaches see Fig. 2 “an active area 210, with a plurality of active trench gates 105 having a double shield field plate 105b, 105c in the active area 210” “active trench gates 105 each have a polysilicon gate 105a with a gate dielectric layer 105d having a horizontal portion below the polysilicon gate 105a and having a vertical portion between the sidewalls of the polysilicon gate 105a and the pbody region 102 and the source region 103. The double shield field plate 105b, 105c is shown below the gate dielectric layer 105d under the polysilicon gate 105a. The gate dielectric layer 105d when it comprises thermal silicon oxide may be thicker in the horizontal portion above the double shield field plate 105b, 105c (due to a higher thermal oxidation rate for polysilicon relative to single crystal silicon) as compared to its thickness on the vertical portion of the trench sidewall of the pbody region 102 and the source region 103” “a metal contact 118b connecting together the polysilicon gates 105a of the active trench gates 105”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tsujimura that the masking region is oxide region and that “wherein the gate region comprises a first gate material and a second gate material”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that oxide is commonly used as a mask layer and is easy to use and gives good results as mask and that thermal silicon oxide is known to give excellent results as gate dielectric and polysilicon gate with metal gate contact and a field plate gives good gate control of channel, with good gate conduction and good field control inside the device.
In regard to claim 18 Tsujimura and Kim as combined teaches a method of manufacture [see Tsujimura Fig. 1 is MOSFET, see combination Kim, see that the oxide is the gate insulation for the MOSFET “When a gate-on potential (a potential higher than a gate threshold) is applied to the gate electrodes 26, channels (inverted layers) are generated in the body regions 32 in the narrow portions 20b in ranges that are in contact with the lateral insulating layers 24b, as a result of which the switching element 10 turns on”] for a nonlinear vertical transistor comprising the steps according to claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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