Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 12/21/2023 and IDS filed on 12/21/2023. Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-3, 9-11, and 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (U.S. Pub. No. 2022/0360257 A1).
As per claim 1, Liu discloses:
An arrangement method of signal lines applied to an integrated circuit comprising a plurality of layers, the arrangement method comprising:
arranging a first signal line extending in a first direction in a first layer (See Figure 4B, i.e. 432A, 453A, 434A & Para [0044]);
arranging a second signal line extending in a second direction perpendicular to the first signal line in a second layer adjacent to the first layer (See Figure 4B, i.e. 422A, 4224A, 426A & Para [0044]); and
arranging a metal oxide semiconductor (MOS) capacitor below a region where the first signal line is arranged (See Para [0044]-[0046], i.e. the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B in a cutting plane A-A′…terminal-conductor 434A extends in the Y-direction and intersects the active-region structure 80n…the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B include the NMOS transistor 51N and various capacitors that form the MIM capacitor 55A in FIG. 4A –[prior art form the MOS transistor for the capacitance in active region 80n (See Figure 80n) , which is at the substrate and is below the first line as cited]),
wherein a signal, which has a voltage lower than that of a signal flowing through the second signal line, flows through the first signal line (See Figure 4Bi.e. VSSA and VDDL is lower than VDDH of the first line, See Para [0043]-[0053]).
As per claim 2, Liu discloses all of the features of claim 1 as discloses above wherein Liu also discloses wherein the arranging of the MOS capacitor comprises arranging a gate region of the MOS capacitor below a region where the first signal line crosses the second signal line (See Para [0045]-[0046], i.e. gate-conductor 453).
As per claim 3, Liu discloses all of the features of claim 1 as discloses above wherein Liu also discloses wherein the arranging of the MOS capacitor comprises arranging a gate region of the MOS capacitor below a region except where the first signal line crosses the second signal line (See Figure 4B, i.e. cT6, See Para [0045]-[0046], i.e. gate-conductor 453, See also Para [0047]-[0053]).
As per claim 9, Liu discloses:
An integrated circuit comprising:
a first layer in which a reference voltage line extending in a first direction is arranged (See Figure 4B, i.e. 432A, 453A, 434A & Para [0044]);
a second layer in which a high voltage signal line extending in a second direction perpendicular to the first direction is arranged (See Figure 4B, i.e. 422A, 4224A, 426A & Para [0044] – [the layer include VDDH, consider as high voltage]); and
a metal oxide semiconductor (MOS) capacitor arranged below a region in which the reference voltage line crosses the high voltage signal line (See Para [0044]-[0046], i.e. the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B in a cutting plane A-A′…terminal-conductor 434A extends in the Y-direction and intersects the active-region structure 80n…the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B include the NMOS transistor 51N and various capacitors that form the MIM capacitor 55A in FIG. 4A –[prior art form the MOS transistor for the capacitance in active region 80n (See Figure 80n) , which is at the substrate and is below the region where line crosses]),
wherein the first layer is arranged below the second layer (See Para [0044], i.e. The horizontal conducting lines 422A, 424A, and 426A extend in the X-direction are fabricated in a first metal layer (such as metal layer M0), See Para [0052] –[prior art arrange the first layer being M0, considered as the lowest layer therefore below the second layer as cited above]).
As per claim 10, Liu discloses all of the features of claim 9 as discloses above wherein Liu also discloses wherein a gate region of the MOS capacitor is arranged below the region, where the reference voltage line crosses the high voltage signal line (See Para [0044]-[0046], i.e. the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B in a cutting plane A-A′…terminal-conductor 434A extends in the Y-direction and intersects the active-region structure 80n…the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B include the NMOS transistor 51N and various capacitors that form the MIM capacitor 55A in FIG. 4A).
As per claim 11, Liu discloses all of the features of claim 10 as discloses above wherein Liu also discloses a first vertical contact configured to electrically connect the gate region of the MOS capacitor to the reference voltage line (See Figure 4B & 4D, i.e. VD, See Para [0056]).
As per claim 14, Liu discloses:
An integrated circuit comprising:
a first layer in which a reference voltage line extending in a first direction is arranged (See Figure 4B, i.e. 432A, 453A, 434A & Para [0044]);
a second layer in which a high voltage signal line extending in a second direction perpendicular to the first direction is arranged (See Figure 4B, i.e. 422A, 4224A, 426A & Para [0044] – [the layer include VDDH, consider as high voltage]);
a metal oxide semiconductor (MOS) capacitor arranged below the reference voltage line (See Para [0044]-[0046], i.e. the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B in a cutting plane A-A′…terminal-conductor 434A extends in the Y-direction and intersects the active-region structure 80n…the capacitive sub-circuit 50A as specified by the layout diagrams in FIG. 4B include the NMOS transistor 51N and various capacitors that form the MIM capacitor 55A in FIG. 4A –[prior art form the MOS transistor for the capacitance in active region 80n (See Figure 80n) , which is at the substrate and is below the first line/reference line as cited]),
wherein the second layer is arranged below the first layer (See Para [0044], i.e. The horizontal conducting lines 422A, 424A, and 426A extend in the X-direction are fabricated in a first metal layer (such as metal layer M0), See Para [0052] –[prior art arrange the first layer being M0, considered as the lowest layer therefore below the second layer as cited above]).
As per claim 15, Liu discloses all of the features of claim 14 as discloses above wherein Liu also discloses wherein a gate region of the MOS capacitor is arranged below a region except where the reference voltage line crosses the high voltage signal line (See Figure 4B, i.e. cT6, See Para [0045]-[0046], i.e. gate-conductor 453, See also Para [0047]-[0053]).
As per claim 16, Liu discloses all of the features of claim 15 as discloses above wherein Liu also discloses a first vertical contact configured to electrically connect the gate region of the MOS capacitor to the reference voltage line (See Figure 4B & 4D, i.e. VD, See Para [0056]).
Allowable Subject Matter
5. Claims 4-8, 12, 13, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claims 4, 12, and/or 17 – wherein claims 5-8 depend on claim 4 – wherein claims 13 depend on claim 12 – wherein claims 18-20 depend on claim 17.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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