DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Introduction
This is a response to the applicant’s filing filed on 12/21/2023. In virtue of this filing, claims 1-20 are currently presented in the instant application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/07/2025 has been considered by Examiner and made of record in the application file.
Drawings
The drawing submitted on 12/21/2023 has been considered by Examiner and made of record in the application file.
Specification
The specification submitted on 12/21/2023 has been considered by Examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 7-8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akbari (US Patent No.: 8,711,831) in view of Haralabidis et al. (US Pub. No.: 2013/0113117, hereinafter, “Haralabidis”).
Regarding claim 1, Akbari teaches a communication integrated circuit (IC) device comprising (see figures 1 and 4, IC transceiver front-end 2, col.4, ln.42-45):
a receive and transmit (Rx/Tx) circuit comprising (see figures 1 and 4, IC transceiver front-end 2, col.4, ln.42-45):
a cascode amplifier (see figure 4, cascode PA 100, col.5, ln.7-10); and
a low-noise amplifier coupled with the cascode amplifier (see figure 4, PA 100, LNA 200, col.5, ln.55); and
a radio frequency (RF) input/output (IO) channel configured to be coupled with a radio antenna (see figure 4, antenna 300, connection point 301, col.4, ln.41-47);
a receive modem coupled with the low-noise amplifier (see figure 1, LNA 200, col.4, 11-16, it is clearly that modem is included modulator and demodulator. Modulator is converting digital signal from base band for transmitting and demodulator is converting incoming analog signal back into digital data for base band); and
a transmit modem coupled with the cascode amplifier (see figure 1, cascode PA 100, col.4, 11-16, it is clearly that modem is included modulator and demodulator. Modulator is converting digital signal from base band for transmitting and demodulator is converting incoming analog signal back into digital data for base band). It is inherent that the system of Akbari is included the modem for modulating signal and demodulating signal.
Making Integral
In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965) (A claim to a fluid transporting vehicle was rejected as obvious over a prior art reference which differed from the prior art in claiming a brake drum integral with a clamping means, whereas the brake disc and clamp of the prior art comprise several parts rigidly secured together as a single unit. The court affirmed the rejection holding, among other reasons, "that the use of a one piece construction instead of the structure disclosed in [the prior art] would be merely a matter of obvious engineering choice."); but see Schenck v. Nortron Corp., 713 F.2d 782, 218 USPQ 698 (Fed. Cir. 1983) (Claims were directed to a vibratory testing machine (a hard-bearing wheel balancer) comprising a holding structure, a base structure, and a supporting means which form "a single integral and gaplessly continuous piece." Nortron argued that the invention is just making integral what had been made in four bolted pieces. The court found this argument unpersuasive and held that the claims were patentable because the prior art perceived a need for mechanisms to dampen resonance, whereas the inventor eliminated the need for dampening via the one-piece gapless support structure, showing insight that was contrary to the understandings and expectations of the art.).
C. Making Separable
In re Dulberg, 289 F.2d 522, 523, 129 USPQ 348, 349 (CCPA 1961) (The claimed structure, a lipstick holder with a removable cap, was fully met by the prior art except that in the prior art the cap is "press fitted" and therefore not manually removable. The court held that "if it were considered desirable for any reason to obtain access to the end of [the prior art’s] holder to which the cap is applied, it would be obvious to make the cap removable for that purpose.").
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It should be noticed that Akbari fails to teach a silicon substrate; and a radio circuit formed on the silicon substrate. However, Haralabidis teaches a silicon substrate; and a radio circuit formed on the silicon substrate (see figure 1, IC transceiver 102, [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Haralabidis into view of Akbari in order to provide monolithic chips to integrated packages with multiple "chiplets" on sophisticated substrates for better performance, power, cost, enabling denser, faster, and more complex Systems-in-Package.
Regarding claim 7, Akbari further teaches the cascode amplifier comprises a power amplifier (see figure 4, cascode PA 100, col.5, ln.7-10).
Regarding claim 8, Akbari teaches a receive and transmit (Rx/Tx) circuit (see figure 1, transceiver IC 2, col.4, ln.43-44) comprising:
a first cascode amplifier comprising (see figure 4, cascode PA 100, col.5, ln.7-10):
a radio frequency (RF) input/output (IO) node configured to output a first transmit signal via an antenna (see figures 3-4, antenna 300, connection point 301, col.4, ln.41-47); and
a first low-noise amplifier node (see figure 3, LNA, node is read on the switch at input LNA);
a low-noise amplifier coupled with the first low-noise amplifier node and having a first low-noise output configured to output a first low noise signal to a first receive channel (see figure 3, LNA, node is read on the switch at input LNA); and
a first transmitter input coupled with the first cascode amplifier and configured to supply a first input signal (transmit signal) from a first transmit channel (TX channel) to the first cascode amplifier (see figures 1 and 4, cascode PA is received the transmit signal at the first transmitter input at preamplifier 140, col.4, ln.12-16);
wherein the first cascode amplifier is configured to generate the first transmit signal based on the first input signal (see figure 4, cascode PA is amplifying the transmit signal inputting at the input of preamplifier 140 and transmit the first transmit signal to the antenna).
It should be noticed that Akbari fails to teach a receive and transmit (Rx/Tx) circuit formed on a silicon substrate. However, Haralabidis teaches a receive and transmit (Rx/Tx) circuit formed on a silicon substrate (see figure 1, IC transceiver 102, [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Haralabidis into view of Akbari in order to provide monolithic chips to integrated packages with multiple "chiplets" on sophisticated substrates for better performance, power, cost, enabling denser, faster, and more complex Systems-in-Package.
Regarding claim 15, Akbari teaches a radio communication circuit (see figure 1, transceiver IC 2, col.4, ln.43-44) comprising:
a cascode amplifier (see figure 4, cascode PA 100, col.5, ln.7-10) and comprising:
a first transistor (see figure 4, transistor 110, col.5, ln.7-10);
a second transistor (see figure 4, transistor 120, col.5, ln.7-19);
an amplifier coupled with the first and second transistors, the amplifier comprising an output (see figures 1 and 4, LNA 200 is coupled to PA 100); and
an input coupled with the second transistor (see figures 1 and 4, input from preamplifier 140 is coupled to transistor 120, col.5, ln.7-19);
a transmit circuit and coupled with the input (see figure 1, transmit path is
included DSP, D/A and mixer 500); and
a receive circuit coupled with the output (see figure 1, receiver path is
included mixer 600, A/D and DSP).
It should be noticed that Akbari fails to teach a receive and transmit (Rx/Tx) circuit formed on a silicon substrate. However, Haralabidis teaches a receive and transmit (Rx/Tx) circuit formed on a silicon substrate (see figure 1, IC transceiver 102, [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Haralabidis into view of Akbari in order to provide monolithic chips to integrated packages with multiple "chiplets" on sophisticated substrates for better performance, power, cost, enabling denser, faster, and more complex Systems-in-Package.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akbari (US Patent No.: 8,711,831) in view of Haralabidis et al. (US Pub. No.: 2013/0113117, hereinafter, “Haralabidis”) as applied to claim 1 above, and further in view of Tsai (US Patent No.: 7,420,425).
Regarding claim 2, Akbari and Haralabidis, in combination, fails to teach the cascode amplifier comprises: a first transistor; a second transistor; and an inductor; wherein the first transistor, the second transistor, and the inductor are coupled in series; and wherein the first transistor is coupled with the second transistor via a first node. However, Tsai teaches the cascode amplifier comprises: a first transistor; a second transistor; and an inductor; wherein the first transistor, the second transistor, and the inductor are coupled in series; and wherein the first transistor is coupled with the second transistor via a first node (see figures 2-3, node is between transistor M1 and M2, inductor 340).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Tsai into view of Akbari and Haralabidis in order to provide monolithic chips to integrated packages with multiple "chiplets" on sophisticated substrates for better performance, power, cost, enabling denser, faster, and more complex Systems-in-Package.
Regarding claim 4, Akbari further teaches the transmit modem is coupled with a gate of the second transistor (see figures 1 and 4, IC transceiver 2, two NMOSFET transistors 110 and 120, input 122 is connected at gate transistor 120, col.5, ln.7-15, it is clearly seen that the transmit signal is modulated).
Claim(s) 3, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akbari (US Patent No.: 8,711,831) in view of Haralabidis et al. (US Pub. No.: 2013/0113117, hereinafter, “Haralabidis”) and further in view of Tsai (US Patent No.: 7,420,425) as applied to claims 1, 8 and 15 above, and further in view of Xu (US Patent No.: 10,735,044).
Regarding claims 3 and 16, Akbari, Haralabidis and Tsai, in combination, fails to teach the low-noise amplifier includes an input coupled with the first node. However, Xu teaches the low-noise amplifier includes an input coupled with the first node (see figure 2, LNA 208, M1 and M0, N3 is node).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into view of Akbari, Haralabidis and Tsai in order to support multi operation.
Regarding claim 9, Akbari and Haralabidis, in combination, fails to teach the first cascode amplifier further comprises a first inductor coupled in series with a first transistor and with a second transistor; wherein the first inductor and the first transistor are coupled in series via the RF IO node; and wherein the first transistor and the second transistor are coupled in series via node. However, Tsai teaches the first cascode amplifier further comprises a first inductor coupled in series with a first transistor and with a second transistor; wherein the first inductor and the first transistor are coupled in series via the RF IO node (input at output matching network 16); and wherein the first transistor and the second transistor are coupled in series via node (see figure 3, inductor 340, first transistor 342, second transistor 344, node between first transistor 342 and second transistor 344).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Tsai into view of Akbari and Haralabidis in order to provide monolithic chips to integrated packages with multiple "chiplets" on sophisticated substrates for better performance, power, cost, enabling denser, faster, and more complex Systems-in-Package.
Akbari, Haralabidis and Tsai, in combination, fails to teach the first transistor and the second transistor are coupled in series via the first low-noise amplifier node. However, Xu teaches the first transistor and the second transistor are coupled in series via the first low-noise amplifier node (see figure 2, LNA 208, M1 and M0, N3 is node).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into view of Akbari, Haralabidis and Tsai in order to support multi operation.
Claim(s) 5 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akbari (US Patent No.: 8,711,831) in view of Haralabidis et al. (US Pub. No.: 2013/0113117, hereinafter, “Haralabidis”) and further in view of Tsai (US Patent No.: 7,420,425) as applied to claims 1 and 15 above, and further in view of Liang et al. (US Pub. No.: 2023/0291431).
Regarding claim 5, Akbari, Haralabidis and Tsai, in combination, fails to teach a control transistor coupled in series between a voltage source and a gate of the first transistor. However, Liang teaches a control transistor coupled in series between a voltage source and a gate of the first transistor (see figure 6, switch 155, NAND gate 165, [0143]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Liang into view of Akbari, Haralabidis and Tsai in order to control the switch on/off operation.
Regarding claim 17, Tsai further teaches the cascode amplifier further comprises an inductor coupled in series with the first transistor via a radio frequency (RF) input/output (IO) node; and wherein the RF IO node is configured to be coupled with a radio antenna (see figure 3, inductor 340, first transistor 342, second transistor 344, node between first transistor 342 and second transistor 344, it is clearly seen that the output matching network 16 is connecting to antenna for transmitting, col.3, ln.1-8).
Regarding claim 18, Akbari further teaches a controller coupled with the transmit circuit and configured to control the transmit circuit to transmit an input signal to the input to cause the RF IO node to output a transmission signal via the radio antenna (see figure 1, DSP 900, ln.32-37).
Regarding claim 19, Akbari further teaches the controller is further coupled with the receive circuit and configured to control the receive circuit to receive a transmitted signal from the radio antenna (see figure 1, DSP 900, ln.32-37).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akbari (US Patent No.: 8,711,831) in view of Haralabidis et al. (US Pub. No.: 2013/0113117, hereinafter, “Haralabidis”), Tsai (US Patent No.: 7,420,425) and further in view of Liang et al. (US Patent No.: 7,420,425) as applied to claim 1 above, and further in view of Joo et al. (US Patent No.: 7,103,126).
Regarding claim 6, Liang teaches a control transistor (see figure 6, switch 155, NAND gate 165, [0143]). Akbari, Haralabidis, Tsai and Liang, in combination, fails to teach the control transistor is further coupled in parallel with a resistor. However, Joo teaches control transistor is further coupled in parallel with a resistor (see figure 6, transistor 608, resistor 606, col.8, ln.57-67).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Joo into view of Akbari, Haralabidis, Tsai and Liang in order to offer the primary advantage of current balancing and thermal stability.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akbari (US Patent No.: 8,711,831) in view of Haralabidis et al. (US Pub. No.: 2013/0113117, hereinafter, “Haralabidis”), Tsai (US Patent No.: 7,420,425) and further in view of Xu (US Patent No.: 10,735,044) as applied to claim 8 above, and further in view of Chen et al. (US Patent No.: 7,843,269).
Regarding claim 14, Akbari, Haralabidis, Tsai and Xu, in combination, fails to teach the first transmitter input is coupled in series with a capacitor and with a gate of the second transistor. However, Chen teaches the first transmitter input is coupled in series with a capacitor and with a gate of the second transistor (see figures 2-3, first common source amplifier 32, transistor M1, capacitor, col.3, ln.12-15).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Chen into view of Akbari, Haralabidis, Tsai and Xu in order to offer the primary advantage of current balancing and thermal stability.
Allowable Subject Matter
Claims 10-13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art made of record fails to clearly teach or fairly suggest the feature of a first control transistor coupled in parallel with a first control resistor; and wherein the first control transistor and the first control resistor are coupled between a control voltage and a gate of the first transistor.
Regarding claim 20, the prior art made of record fails to clearly teach or fairly suggest the feature of a control resistor coupled with a gate of the first transistor; and a third transistor coupled in parallel with the control resistor and coupled with the controller; wherein the controller is further configured to control the third transistor into a conduction mode during control of the transmit circuit to transmit the input signal to the input.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuan A. Pham whose telephone number is (571) 272-8097, the fax number is (571) 273-8097 and the email is tuan.pham01@uspto.gov. The examiner can normally be reached on Monday through Friday, 8:30 AM-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yuwen (Kevin) Pan can be reached on (571) 272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUAN PHAM/ Primary Examiner, Art Unit 2649