DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, 8-9, 11-16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Keil, US PGPub 2020/0050396.
With respect to claim 1, Keil teaches a data processing system, comprising:
a data processor for issuing memory commands (par. 96 and fig. 6, memory controller 610) including a first memory command that accesses data of a first size (pars. 97-98, mask write memory request 630 containing an amount of data); and
a memory operative to transfer data of the first size by separating a first portion of data from a second portion of data by a data gap (pars. 97-100, the mask write request is separated into three mask write commands, each containing data, separated by gaps. Referring to fig. 7, the first mask write command W(p1), corresponding the first portion of data, is separated by a timing gap 754 from the second mask write command W(p1) 741, corresponding to the second portion of data),
wherein the data processor is operable to selectively prioritize and issue a second memory command after issuing the first memory command at a time that fills the data gap (par. 100, the timing gap 751 is filled, in part, by a first memory command A(p2) 760, as illustrated in fig. 7. Pars. 79-80 describe the selection criteria to prioritize which commands to choose to issue fill the data gap).
With respect to claim 2, Keil teaches the data processing system of claim 1, wherein the second memory command accesses data of one of the first size and a second size smaller than the first size (pars. 76-77, the write mask request is the first size, which is split into three write commands, while the commands filling the gap each correspond to just one command, so the commands filling the gap have a second size smaller than the first size).
With respect to claim 3, Keil teaches the data processing system of claim 1, wherein the data processor comprises a memory controller, and the memory controller comprises:
a command queue (par. 75 and fig. 7, command buffer 750) for storing a plurality of memory access requests including first memory access requests that access data of the first size and second memory access requests that access data of a second size (pars. 76-77 and fig. 7, the command queue contains the mask write request of the first size, which corresponds to the three write commands W(p1) 740, W(p1) 741 and W(p1) 742), as well as second memory access requests, such as A(p2) 760, A(p3) 770, R(p2) 761, A(p4) 780, and R(p3) 771, each the second size of a single command); and
an arbiter (par. 77, control circuit 615) for selecting accesses from the command queue according to a plurality of arbitration rules, wherein the arbiter generates the second memory command for issuance during the data gap (pars. 77-78, the control circuit 615 schedules other memory access command to fill the timing gaps between successive ones of write commands W(p1) 740-742. Pars. 79-80 describe the arbitration rules/selection criteria to prioritize which commands to choose to issue to fill the data gap).
With respect to claim 5, Keil teaches the data processing system of claim 3, wherein the memory controller is further operative to:
issue a third memory command that accesses data at a time following the first memory command such that the memory conducts data of the second memory command during a subsequent data gap (par. 99 and fig. 7, timing gap 755 is the subsequent gap, and R(p2) 761 is a third memory command issued to fill the timing gap.).
With respect to claim 6, Keil teaches the data processing system of claim 5, wherein the second memory command accesses data of one of the first size and the second size (par. 79, the command R(p2) is a single command, so corresponds to the second size).
With respect to claim 8, Keil teaches a data processor, comprising:
a first memory accessing agent capable of generating a first memory access request of a first size (pars. 97-98, mask write memory request 630 is the first memory access request. As described in par. 35, the memory access requests are received from a processing circuit included in a computing system that is coupled to the memory system. This processing circuit corresponds to the first memory accessing agent of the claim); and
a memory controller (par. 96 and fig. 6, memory controller circuit 610) comprising:
a command queue for storing a plurality of memory access requests (par. 75 and fig. 7, command buffer 750); and
an arbiter (par. 77, control circuit 615) for selecting among the plurality of memory access requests stored in the command queue according to a plurality of arbitration rules (pars. 77-78, the control circuit 615 schedules other memory access command to fill the timing gaps between successive ones of write commands W(p1) 740-742. Pars. 79-80 describe the arbitration rules/selection criteria to prioritize which commands to choose to issue to fill the data gap),
wherein the memory controller is operative to prioritize and issue a first memory command that accesses data of the first size to a memory that is operative to transfer the data of the first size by separating a first portion of data from a second portion of data by a data gap (pars. 97-100, the mask write request is separated into three mask write commands, each containing data, separated by gaps. Referring to fig. 7, the first mask write command W(p1), corresponding the first portion of data, is separated by a timing gap 754 from the second mask write command W(p1) 741, corresponding to the second portion of data),
wherein the memory controller is further operative to selectively issue a second memory command after issuing the first memory command at a time that fills the data gap (par. 100, the timing gap 751 is filled, in part, by a first memory command A(p2) 760, as illustrated in fig. 7. Pars. 79-80 describe the selection criteria to prioritize which commands to choose to issue fill the data gap).
With respect to claim 9, Keil teaches the data processor of claim 8, wherein the second memory command accesses data of one of the first size and a second size smaller than the first size (pars. 76-77, the write mask request is the first size, which is split into three write commands, while the commands filling the gap correspond to just one command, so the commands filling the gap have a second size smaller than the first size).
With respect to claim 11, Keil teaches the data processor of claim 8, wherein the memory controller is further operative to:
selectively issue a third memory command that accesses data at a time following an issuance of the first memory command such that the memory conducts data of the third memory command a subsequent the data gap (par. 99 and fig. 7, timing gap 755 is the subsequent gap, and R(p2) 761 is a third memory command issued to fill the timing gap).
With respect to claim 12, Keil teaches the data processor of claim 11, wherein the second memory command accesses data of one of the first size and a second size that is smaller than the first size (pars. 76-77, the write mask request is the first size, which is split into three write commands, while the commands filling the gap correspond to just one command, so the commands filling the gap have a second size smaller than the first size).
With respect to claim 13, Keil teaches the data processor of claim 12, further comprising a graphics controller, wherein the memory controller is operative to issue the third memory command in response to a graphics operation provided by the graphics controller (pars. 100-108, the memory controller 1108, which corresponds to the memory control circuits described previously, issues memory commands in response to commands from graphics processor 1102).
With respect to claim 14, Keil teaches the data processor of claim 8, wherein the first memory accessing agent comprises a central processing unit core complex (par. 104, core complex 1101) that is operative to issue the first memory command in response to a cache line fill operation (pars. 107-108, if the requested data is not currently cached in cache memory 1106, memory cache controller 1105 sends the transaction controller circuit 1109 to fetch the requested data, i.e., a cache line fill operation).
With respect to claim 15, Keil teaches a method, comprising:
generating a first memory access request that accesses data of a first size by a first memory accessing agent (pars. 96-98, mask write memory request 630 is the first memory access request. As described in par. 35, the memory access requests are received from a processing circuit included in a computing system that is coupled to the memory system. This processing circuit corresponds to the first memory accessing agent of the claim);
issuing a first memory command in response to the first memory access request to a memory that transfers data of the first size by separating a first portion of data from a second portion of data by a data gap (pars. 97-100, the mask write request is separated into three mask write commands, each containing data, separated by gaps. Referring to fig. 7, the first mask write command W(p1), corresponding the first portion of data, is separated by a timing gap 754 from the second mask write command W(p1) 741, corresponding to the second portion of data); and
selectively prioritizing and issuing a second memory command after issuing the first memory command at a time that fills the data gap (par. 100, the timing gap 751 is filled, in part, by a first memory command A(p2) 760, as illustrated in fig. 7. Pars. 79-80 describe the selection criteria to prioritize which commands to choose to issue fill the data gap).
With respect to claim 16, Keil teaches the method of claim 15, wherein selectively prioritizing and issuing the second memory command that does not access data comprises:
selectively prioritizing and issuing a memory command that has one of the first size and a second size smaller than the first size (pars. 76-77, the write mask request is the first size, which is split into three write commands, while the commands filling the gap correspond to just one command, so the commands filling the gap have a second size smaller than the first size. Pars. 79-80 describe the selection criteria to prioritize which commands to choose to issue fill the data gap).
With respect to claim 19, Keil teaches the method of claim 15, further comprising:
storing a first plurality of memory access requests including memory access requests having the first size and a second plurality of memory access requests having a second size in a command queue (pars. 76-77 and fig. 7, the command queue contains the mask write request of the first size, which corresponds to the three write commands W(p1) 740, W(p1) 741 and W(p1) 742), as well as second memory access requests, such as A(p2) 760, A(p3) 770, R(p2) 761, A(p4) 780, and R(p3) 771, each the second size of a single command);
selecting accesses from the command queue according to a plurality of arbitration rules (pars. 77-78, the control circuit 615 selects other memory access command to fill the timing gaps between successive ones of write commands W(p1) 740-742. Pars. 79-80 describe the arbitration rules/selection criteria to prioritize which commands to choose to issue to fill the data gap); and
issuing the first memory command to have a first burst length corresponding to the first size, and the second memory command to have a second burst length corresponding to the second size such that data of the second memory command is transferred during the data gap (pars. 77-78, the control circuit 615 issues other memory access command to fill the timing gaps between successive ones of write commands W(p1) 740-742, which have the first burst length corresponding the first size, while the commands filling the gaps have the second burst length of the second size).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keil, as applied to claims 1 and 15 above, in view of Lu et al., US PGPub 2024/0202145, hereafter “Lu.”
With respect to claim 7, Keil teaches all limitations of the parent claim, but fails to teach an LPDDR5 memory. Lu further teaches the data processing system of claim 1, wherein the memory comprises: a low power double data rate, version five (LPDDR5) memory (par. 26).
It would have been obvious to one of ordinary skill in the art, having the teachings of Keil and Lu before him before the earliest effective filing date, to modify the memory access system of Keil with the memory access system of Lu, in order to use a low-power memory device such as a LPDDR5 memory device, to conserve power and preserve battery life, as taught by Lu in par. 15.
With respect to claim 20, Keil teaches the limitations of the parent claim, but fails to teach an LPDDR5 memory. Lu further teaches the method of claim 15, wherein: generating the first memory access request of the first size to a low power double data rate, version five (LPDDR5) memory (par. 34 discloses a memory access request such as a read or write, and par. 26 discloses that the memory may be a LPDDR5 memory).
It would have been obvious to one of ordinary skill in the art, having the teachings of Keil and Lu before him before the earliest effective filing date, to modify the memory access method of Keil with the memory access method of Lu, in order to use a low-power memory device such as a LPDDR5 memory device, to conserve power and preserve battery life, as taught by Lu in par. 15.
Claim(s) 4, 10 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keil as applied to claims 1, 3, 8 and 15 above, in view of Chun et al., US PGPub 2016/0093345, hereafter “Chun.”
With respect to claim 4, Keil teaches all limitations of the parent claims, but fails to teach a burst length history table coupled to the arbiter for storing a history of burst lengths of recently issued memory commands, wherein the arbiter is further operative to select the second memory command in response to the history of burst lengths. Chun further teaches the data processing system of claim 3, wherein the memory controller further comprises:
a burst length history table (par. 39 and fig. 3, traffic shaping rule table) coupled to the arbiter for storing a history of burst lengths of recently issued memory commands (pars. 50-51 and fig. 5, a transaction is generated in step 506, and used to populate the traffic shaping rule table, which, as shown in fig. 3, contains transaction size (burst length), idle time, and corresponding rules),
wherein the arbiter is further operative to select the second memory command in response to the history of burst lengths (pars. 50-51, and fig. 5, in step 512, a next rule is selected and a next transaction of a particular size is selected from the traffic rule shaping table in step 506).
It would have been obvious to one of ordinary skill in the art, having the teachings of Keil and Chun before him before the earliest effective filing date, to modify the memory access system of Keil with the memory access system of Chun, in order to reduce voltage fluctuations on a bus when sending bursts of data, as taught by Chun in pars. 30-32.
With respect to claim 10, Keil teaches all limitations of the parent claim but fails to teach a burst length history table coupled to the arbiter for storing a history of burst lengths of recently issued memory commands, wherein the arbiter is further operative to select the second memory command in response to the history of burst lengths. Chun further teaches the data processor of claim 8, wherein the memory controller further comprises:
a burst length history table coupled to the arbiter (par. 39 and fig.3, traffic shaping rule table) for storing a history of burst lengths of recently issued memory commands (pars. 50-51 and fig. 5, a transaction is generated in step 506, and used to populate the traffic shaping rule table, which, as shown in fig. 3, contains transaction size (burst length), idle time, and corresponding rules),
wherein the arbiter is further operative to select the second memory command in response to the history of burst lengths (pars. 50-51, and fig. 5, in step 512, a next rule is selected and a next transaction of a particular size is selected from the traffic rule shaping table in step 506).
It would have been obvious to one of ordinary skill in the art, having the teachings of Keil and Chun before him before the earliest effective filing date, to modify the memory access system of Keil with the memory access system of Chun, in order to reduce voltage fluctuations on a bus when sending bursts of data, as taught by Chun in pars. 30-32.
With respect to claim 17, Keil teaches the limitations of the parent claims but fails to teach maintaining a history of burst lengths of recently issued memory commands and issuing the second memory command that does not access data during the data gap indicated by the history. Chun further teaches the method of claim 15, further comprising:
maintaining a history of burst lengths of recently issued memory commands (pars. 50-51 and fig. 5, a transaction is generated in step 506, and used to populate the traffic shaping rule table, which, as shown in fig. 3, contains transaction size (burst length), idle time, and corresponding rules); and
issuing the second memory command that does not access data during the data gap indicated by the history (pars. 50-51, and fig. 5, in step 512, a next rule is selected and a next transaction of a particular size is selected from the traffic rule shaping table in step 506, the rule shaping table also including idle time (data gap)).
It would have been obvious to one of ordinary skill in the art, having the teachings of Keil and Chun before him before the earliest effective filing date, to modify the memory access method of Keil with the memory access method of Chun, in order to reduce voltage fluctuations on a bus when sending bursts of data, as taught by Chun in pars. 30-32.
With respect to claim 18, Keil and Chun teach the limitations of the parent claim. Chun further teaches the method of claim 17, wherein maintaining the history of burst lengths comprises:
storing the history of the burst lengths in a burst length history table (par. 39 and fig. 3, traffic shaping rule table, storing transaction size (burst length)).
Response to Arguments
Applicant's arguments filed 10/16/2025 have been fully considered but they are not persuasive. Applicant argues on pages 7-8 that the Keil reference discloses that Control Circuit 615 of Memory Controller 610 performs the function of separating a Mask Write Memory Request 630 into three mask write commands, and therefore does not disclose a data processor that interacts with a memory that performs the function. However, looking at the disclosed fig. 6, while it is true that Control Circuit 615 is part of Memory Controller 610, Memory Controller 610 is part of Memory System 600, which the examiner is considering the memory of the claim. In other words, the functions of the control circuit, as part of the memory, are a function of the memory. Applicant also argues the claimed separation of data and Weil’s failure to disclose that separation of data and instead spaces the write mask commands. As can be seen in the reproduced fig. 6 of Weil, W(p2) 640, W(p2) 641 and W(p2) 642 are shown with separation of data inside of command buffer 650. This isn’t just spacing of commands, it is separating data inside a buffer. Applicant’s arguments regarding independent claim 8 and independent claim 15 are similar to those for independent claim 1, and are not persuasive for the same reasons. Applicant additionally argues Weil does not disclose prioritizing operations and filling a data gap, but provides no reasoning behind this argument. With respect to these argument, Applicant fails to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Applicant’s arguments on pages 9-10 are directed towards Lu allegedly failing to teach a memory controller that can “fill the gap” caused by using the LPDDR5 with a burst length of 32 in 4:1 mode. However, Lu is only cited to teach “wherein the memory comprises: a low power double data rate, version five (LPDDR5) memory.” The Keil reference teaches filling a data gap, as discussed above, with respect to claim 1.
Applicant’s arguments on page 10 regarding claims 4, 10, 17, and 18 are directed towards Keil allegedly not teaching the parent independent claims 1, 8 and 15. These arguments are moot, as Keil teaches the independent claims, as discussed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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