DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claims 1, 5-6, 9, 12, 14, 16, and 18-20 have been amended.
This action is Final.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 9, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Conner et al. (hereinafter as O’Conner) PGPUB 2003/0056125, and further in view of Rajwan et al. (hereinafter as Rajwan) PGPUB 2023/0101217.
As per claim 1, O’Conner teaches a system, comprising:
a plurality of component circuits [FIG. 1 processors P1-P8];
a plurality of power sources, wherein at least two of the plurality of power sources are configured to supply power to respective sets of the plurality of component circuits [FIG. 1 PS1-PS4 and FIG. 2A: (PS1 and PS2 are each configured to supply power to corresponding processors)]; and
a power splitter circuit coupled to the plurality of component circuits [FIG. 1 and 0038-0041, 0043, and 0047-0051: (power management engine 13 (power splitter circuit) is coupled to processors because it detects processor changes and controls which power supply to operate to provide the power to the processor)], wherein the power splitter circuit are configured to store a mapping between ones of the plurality of component circuits and ones of the plurality of power sources [FIG. 2A, and 0039-0043: (power management engine 13 stores a power supply table 34 which lists processors that a particular power supply provides power to)], wherein the power splitter circuit is configured to:
determine, based on the mapping, which of the plurality of power sources supply power to the particular component circuit [0039 and 0071: (examines the supply tables 28 and demand tables 30 to determine if additional power supplies are needed to power the processor)];
allocate, to the particular component circuit, power from power budgets specific to the determined power sources [0043 and 0047-0049: (using the tables, loading capabilities of the power supplies are determined to see if additional power supplies are necessary; after determination of adequate power from the loading capabilities (power budget of the power sources), power is provided to processor 16c)].
O’Conner does not explicitly teach the power splitter circuit includes one or more programmable registers; wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source; receive, from a particular one of the plurality of component circuits, a request for power credits to obtain power; and allocate, to the particular component circuit, a set of power credits from power budgets specific to the determined power sources.
Rajwan teaches a power split circuit that controls power consumption of component circuits based on power allocated to the component circuits. Rajwan is thus similar to O’Conner because they control the power to multiple components from multiple power sources. Rajwan further teaches the power splitter circuit includes one or more programmable registers [0024: power policy registers 18A-N]; wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source [0027: (represented as plurality of credits)]; receive, from a particular one of the plurality of component circuits, a request for power credits to obtain power [0060: requests]; and allocate, to the particular component circuit, a set of power credits from power budgets specific to the determined power sources [0061-0062 and 0078]. Rajwan teaches the use of power credits in allocating and assigning power to components.
The combination of O’Conner with Rajwan leads to the use of power credits and rate control circuits in O’Conner’s power management engines or resource management engines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Rajwan’s teachings of power credits and rate control circuits in O’Conner. One of ordinary skill in the art would have been motivated to use power credits and rate control circuits in O’Conner because it is a power management mechanism that can be cost effective when managing multiple power sources [Rajwan 0020].
As per claim 9, O’Conner and Rajwan teach the system of claim 1, wherein the particular component circuit includes a rate control circuit configured to manage power consumption in the particular component circuit based on the set of power credits [Rajwan 0027].
As per claim 12, O’Conner teaches a method, comprising:
accessing, by a power splitter circuit [FIG. 1 power management engine 13], information accessible to the power splitter circuit, wherein the information specifies which ones of a plurality of power sources of the system are configured to supply power to which ones of the plurality of component circuits [FIG. 2A, and 0039-0043: (power management engine 13 stores a power supply table 34 which lists processors (plurality of component circuits) that a particular power supply provides power to)];
determining, by the power splitter circuit based on the information, that multiple ones of the plurality of power sources are configured to supply power to the particular component circuits [0032, 0041, and 0047-0049: (power supplies are turned on as needed based on the power demand of the processor component circuits; if additional power is needed, multiple power supplies may be turned on based on the table 34 to provide power to a processor component)]; and
allocating, by the power splitter circuit, power to the particular component circuit based on respective power budgets of the multiple power sources [0043 and 0047-0049: (using the tables, loading capabilities of the power supplies are determined to see if additional power supplies are necessary; after determination of adequate power, power is provided to processor 16c)].
O’Conner does not explicitly teach receiving, by the power splitter circuit, a request for power credits to obtain power, wherein the request is received from a particular one of a plurality of component circuits managed by the power splitter circuit; information from one or more programmable registers accessible to the power splitter circuit; wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source; and allocating a set of power credits.
Rajwan teaches a power split circuit that controls power consumption of component circuits based on power allocated to the component circuits. Rajwan is thus similar to O’Conner because they control the power to multiple components from multiple power sources. Rajwan further teaches receiving, by the power splitter circuit, a request for power credits to obtain power, wherein the request is received from a particular one of a plurality of component circuits managed by the power splitter circuit [0060: requests]; information from one or more programmable registers accessible to the power splitter circuit [0024 and 0030-0031: power policy registers 18A-N]; wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source [0027: (represented as plurality of credits)]; and allocating a set of power credits [0061-0062 and 0078]. Rajwan teaches the use of power credits in allocating and assigning power to components.
The combination of O’Conner with Rajwan leads to the use of power credits and rate control circuits in O’Conner’s power management engines or resource management engines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Rajwan’s teachings of power credits and rate control circuits in O’Conner. One of ordinary skill in the art would have been motivated to use power credits and rate control circuits in O’Conner because it is a power management mechanism that can be cost effective when managing multiple power sources [Rajwan 0020].
Claim 18 is similar in scope 1 to claim as addressed above and is thus rejected under the same rationale. O’Conner and Rajwan further teach a plurality of integrated circuit dies coupled together [Rajwan 0079 and 0111]; and access the mapping from the one or more programmable registers [Rajwan 0031: (policy in the registers are referred to)].
Claim(s) 1-6, 9, and 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Conner et al. (hereinafter as O’Conner) PGPUB 2003/0056125, and further in view of Piszczek et al. (hereinafter as Piszczek) USPAT 9,477,279, with evidence by Durham et al. (hereinafter as Durham) PGPUB 2020/0142462.
As per claim 1, O’Conner teaches a system, comprising:
a plurality of component circuits [FIG. 1 processors P1-P8];
a plurality of power sources, wherein at least two of the plurality of power sources are configured to supply power to respective sets of the plurality of component circuits [FIG. 1 PS1-PS4 and FIG. 2A: (PS1 and PS2 are each configured to supply power to corresponding processors)]; and
a power splitter circuit coupled to the plurality of component circuits [FIG. 1 and 0038-0041, 0043, and 0047-0051: (power management engine 13 (power splitter circuit) is coupled to processors because it detects processor changes and controls which power supply to operate to provide the power to the processor)], wherein the power splitter circuit are configured to store a mapping between ones of the plurality of component circuits and ones of the plurality of power sources [FIG. 2A, and 0039-0043: (power management engine 13 stores a power supply table 34 which lists processors that a particular power supply provides power to)], wherein the power splitter circuit is configured to:
determine, based on the mapping, which of the plurality of power sources supply power to the particular component circuit [0039 and 0071: (examines the supply tables 28 and demand tables 30 to determine if additional power supplies are needed to power the processor)];
allocate, to the particular component circuit, power from power budgets specific to the determined power sources [0043 and 0047-0049: (using the tables, loading capabilities of the power supplies are determined to see if additional power supplies are necessary; after determination of adequate power from the loading capabilities (power budget of the power sources), power is provided to processor 16c)].
O’Conner does not explicitly teach the power splitter circuit includes one or more programmable registers; wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source; receive, from a particular one of the plurality of component circuits, a request for power credits to obtain power; and allocate, to the particular component circuit, a set of power credits from power budgets specific to the determined power sources.
Piszczek teaches performing power management in a computing device with multiple power supplies. Piszczek is thus similar to O’Conner. Piszczek further teaches wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source [col. 12 lines 44-48, col. 13 lines 6-10, col. 13 lines 33-35: (power credits are allocated according to a power budget from power sources to computing devices)]; receive, from a particular one of the plurality of component circuits, a request for power credits to obtain power [col. 5 lines 19-24, col. 13 lines 27-30: (make request for more power credits)]; and allocate, to the particular component circuit, a set of power credits from power budgets specific to the determined power source2s [col. 14 lines 5-14: (in response, provide extra power credit and col. 9 lines 48-53)]. Piszczek teaches representing power from power sources as power credits and providing excess power credits to other devices based on requests.
The combination of O’Conner with Piszczek leads to the use of power credits and rate control circuits in O’Conner’s power management engines or resource management engines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Piszczek’s teachings of power credits and rate control circuits in O’Conner. One of ordinary skill in the art would have been motivated to use power credits in O’Conner because it allows for more efficient usage of power supplies based on loading levels since some loads may not need much power than others at a given time [Piszczek col 2 lines 50-56].
O’Conner and Piszczek do not teach the power splitter circuit includes one or more programmable registers. O’Conner’s power management engine 13 stores various tables and mappings, but it does not mention whether they are stored in a register.
However, it is well known to one of ordinary skill in the art to use a register for storage of information for a processing element. Thus it would be obvious to one of ordinary skill in the art for O’Conner and Piszczek to utilize a register for storing the power supply table within the power management engine (which is a processing element). One of ordinary skill in the art would have been motivated to use a register in O’Conner and Piszczek because registers are fast, small, and easily accessed by the power management engine/processing element compared to other types of storages.
Durnham shows as evidence that a table may be stored in a register of a controller [0043].
As per claim 2, O’Conner and Piszczek teach the system of claim 1, wherein multiple power sources of the plurality of power sources are each configured to supply a respective, different amount of power [O’Conner 0042: (it is not necessary for power supplies 22 to be identical), 0047, and 0078: (power supplies are selected for powering on based on efficiency, and thus different power supplies may have different amounts of power contributions to the processor components)].
As per claim 3, O’Conner and Piszczek teach the system of claim 1, wherein the power splitter circuit is configured to: determine, based on the power budgets specific to the determined power sources and a set of power split policies, a plurality of amounts of power suppliable by the determined power sources to a particular component circuit; select a minimum of the plurality of amounts of power; and allocate the minimum amount of power to the particular component circuit via the set of power credits [O’Conner 0073, 0076, and 0078: (checks each power supply and evaluate its efficiency at the current loading requirements, and only the power supply with the best matched is used; using the most efficient power supply for a given load means using the minimum amount of power to power a load) and Piszczek col. 12 lines 17-34: (allocated minimum portion of power; return any extra power credits; thus the allocated minimum power is provided through power credits)].
As per claim 4, O’Conner and Piszczek teach the system of claim 3, wherein the power splitter circuit is configured to reallocate, from at least one of the multiple power sources, an unused portion of power to a corresponding power budget in a next power allocation cycle [O’Conner FIG. 4, 0050-0052, and 0074: (each decision period (power allocation cycle) determines the power available from the power supplies including any unused portions of a power supply, such as from a previous cycle)].
As per claim 5, O’Conner and Piszczek teach the system of claim 3, wherein the power splitter circuit is configured to apply a same power split policy to the respective power budgets of the determined power sources [O’Conner 0071-0073 and FIG. 4: (the policy of FIG. 4 is applied to all the power sources and their corresponding power budgets)].
As per claim 6, O’Conner and Piszczek teach the system of claim 1, wherein the power splitter circuit is configured to allocate power credits to at least two different component circuits that are coupled to different power sources [O’Conner FIG. 1 and FIG. 2A, and 0041: (power management engine allocates power from different power sources to different processors) and Piszczek col. 13 lines 6-10].
As per claim 9, O’Conner and Piszczek teach the system of claim 1, wherein the particular component circuit includes a rate control circuit configured to manage power consumption in the particular component circuit based on the set of power credits [Piszczek col. 12 lines 48-51 and col. 14 lines 10-14].
As per claim 12, O’Conner teaches a method, comprising:
accessing, by a power splitter circuit [FIG. 1 power management engine 13], information accessible to the power splitter circuit, wherein the information specifies which ones of a plurality of power sources of the system are configured to supply power to which ones of the plurality of component circuits [FIG. 2A, and 0039-0043: (power management engine 13 stores a power supply table 34 which lists processors (plurality of component circuits) that a particular power supply provides power to)];
determining, by the power splitter circuit based on the information, that multiple ones of the plurality of power sources are configured to supply power to the particular component circuits [0032, 0041, and 0047-0049: (power supplies are turned on as needed based on the power demand of the processor component circuits; if additional power is needed, multiple power supplies may be turned on based on the table 34 to provide power to a processor component)]; and
allocating, by the power splitter circuit, power to the particular component circuit based on respective power budgets of the multiple power sources [0043 and 0047-0049: (using the tables, loading capabilities of the power supplies are determined to see if additional power supplies are necessary; after determination of adequate power, power is provided to processor 16c)].
O’Conner does not explicitly teach receiving, by the power splitter circuit, a request for power credits to obtain power, wherein the request is received from a particular one of a plurality of component circuits managed by the power splitter circuit; information from one or more programmable registers accessible to the power splitter circuit; wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source; and allocating a set of power credits.
Piszczek teaches a power split circuit that controls power consumption of component circuits based on power allocated to the component circuits. Piszczek is thus similar to O’Conner because they control the power to multiple components from multiple power sources. Piszczek further teaches receiving, by the power splitter circuit, a request for power credits to obtain power, wherein the request is received from a particular one of a plurality of component circuits managed by the power splitter circuit [col. 5 lines 19-24, col. 13 lines 27-30: (make request for more power credits)]; wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source [0027: (represented as plurality of credits)]; and allocating a set of power credits [col. 12 lines 44-48, col. 13 lines 6-10, col. 13 lines 33-35: (power credits are allocated according to a power budget from power sources to computing devices)]. Rajwan teaches the use of power credits in allocating and assigning power to components [col. 14 lines 5-14: (in response, provide extra power credit and col. 9 lines 48-53)]. Piszczek teaches representing power from power sources as power credits and providing excess power credits to other devices based on requests.
The combination of O’Conner with Piszczek leads to the use of power credits and rate control circuits in O’Conner’s power management engines or resource management engines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Piszczek’s teachings of power credits and rate control circuits in O’Conner. One of ordinary skill in the art would have been motivated to use power credits in O’Conner because it allows for more efficient usage of power supplies based on loading levels since some loads may not need much power than others at a given time [Piszczek col 2 lines 50-56].
O’Conner and Piszczek do not teach information from one or more programmable registers accessible to the power splitter circuit. O’Conner’s power management engine 13 stores and accesses various tables and mappings, but it does not mention whether they are stored in a register.
However, it is well known to one of ordinary skill in the art to use a register for storage of information for a processing element. Thus it would be obvious to one of ordinary skill in the art for O’Conner and Piszczek to utilize a register for storing the power supply table within the power management engine (which is a processing element). One of ordinary skill in the art would have been motivated to use a register in O’Conner and Piszczek because registers are fast, small, and easily accessed by the power management engine/processing element compared to other types of storages.
Durnham shows as evidence that a table may be stored in a register of a controller [0043].
As per claim 13, O’Conner and Piszczek teach the method of claim 12, wherein at least two of the multiple power sources are different types and are each configured to supply a different amount of power to the particular component circuit [O’Conner 0042: (it is not necessary for power supplies to be identical) and 0047, and 0078: (power supplies are selected for powering on based on efficiency, and thus different power supplies may have different amounts of power contributions to the processor components due their differences in efficiencies); furthermore, other prior art such as Keskin also teaches different voltage regulator types and different amounts of power supplied)].
Claim 14 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
As per claim 15, O’Conner and Piszczek teach the method of claim 12, further comprising: providing, by the power splitter circuit and to a different power splitter circuit that manages a different component circuit, power credits corresponding to unused power [col. 11 lines 35-36: (control of power credits may be distributed between control nodes (power splitter circuit and different power splitter circuits) and col. 9 lines 48-52: (power credits are donations of allocated power that is not used)], wherein the different power splitter circuit is configured to allocate, based on the power credits, additional power from the multiple power sources to the different component circuit [col. 14 lines 5-14: (extra power credits are provided to provide additional power allocations to a device)].
As per claim 16, O’Conner and Piszczek teach the method of claim 12, wherein the allocating of the power to the particular component circuit includes: applying a power split policy to a power budget of a particular one of the multiple power sources to split suppliable power of the particular power source amongst component circuits that receive power from the particular power source, wherein the power allocated to the particular component circuit is based on the split suppliable power [O’Conner FIG. 2A and FIG. 2B, 0049-0051, and 0078: (each power supply may serve multiple processors, and the division of power from a particular power supply among the processing loads is based on the demand of the processors and whether the capabilities of the power supply to meet demand and redundancy requirements (power optimization policy and redundancy requirements); portions of power from a power supply will be provided to one processor while other portions will be provided to another processor)].
Claim(s) 7 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Conner et al. (hereinafter as O’Conner) PGPUB 2003/0056125, Piszczek et al. (hereinafter as Piszczek) USPAT 9,477,279, and further in view of Gupta et al. (hereinafter as Gupta) USPAT 11,079,824.
As per claim 7, O’Conner and Piszczek teach the system of claim 1.
O’Conner and Piszczek do not teach further comprising: a plurality of integrated circuit dies coupled together, wherein the plurality of integrated circuit dies include: a first integrated circuit die comprising the plurality of component circuits and the power splitter circuit; and a second integrated circuit die comprising another plurality of component circuits and another power splitter circuit; wherein at least two of the plurality of power sources are configured to supply power to a same integrated circuit die of the plurality of integrated circuit dies.
Gupta teaches a current distribution component that receives power from multiple power domains and distributing the power to components. Gupta is thus similar to O’Conner and Piszczek. Gupta further teaches a plurality of integrated circuit dies coupled together [col. 5 lines 30-33: (circuit may be a set of integrated circuits)], wherein the plurality of integrated circuit dies include: a first integrated circuit die comprising the plurality of component circuits and the power splitter circuit [FIG. 2 integrated circuit 250 with components 281-283]; a second integrated circuit die comprising another plurality of component circuits and another power splitter circuit [col. 5 lines 30-33: (circuit may be a set of integrated circuits, and it is obvious the second die may have a structure similar to the first die with multiple power domains providing power to a current distribution component)]; and wherein at least two of the plurality of power sources are configured to supply power to a same integrated circuit die of the plurality of integrated circuit dies [FIG. 2: (plurality of power domains supply power to the same integrated circuit 250)].
The combination of O’Conner and Piszczek with Gupta leads to implementation of O’Conner’s teachings at an IC chip level where multiple power domains provide power to a current distribution component of an IC and the current distribution component utilizes its lookup tables to determine what components to provide power to, and using multiple IC chips.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Gupta’s teachings of multiple IC chips in which multiple power domains provide power to a current distribution component of each IC chip for distribution to components of the IC chip in O’Conner and Piszczek. Gupta teaches application of O’Conner’s teachings at an IC chip level. One of ordinary skill in the art would have been motivated to utilize Gupta’s teachings and implement O’Conner and Piszczek’s teachings at an IC chip level because it allows for efficient management of power sources an IC chip level and would reduce waste in terms of power consumption.
As per claim 18, Gupta teaches a non-transitory computer-readable medium [col. 3 lines 67 – col. 4 line 3] having stored thereon design information specifying a circuit design in a format recognizable by a fabrication system that is configured to use the design information to fabricate a hardware integrated assembly that comprises:
a plurality of integrated circuit dies coupled together [col. 5 lines 30-33: (a circuit (such as integrated circuit of FIG. 1) may include a set of integrated circuits)]; and
a plurality of power sources, wherein at least two of the plurality of power sources are configured to supply power to a particular one of the plurality of integrated circuit dies [FIG. 2, col. 8 lines 7 – 44, : (a plurality of power domains supply power for distribution to a particular integrated circuit)],
wherein the particular integrated circuit die comprises a plurality of component circuits [FIG. 2: (integrated circuit comprises a plurality of components 281-283)] coupled to a power splitter circuit [FIG. 2 current distribution component 220]
wherein the power splitter circuit is configured to:
allocate power to a given one of the plurality of component circuits based on one or more power budgets of one or more power sources [col. 9 lines 53-57: (electrical metric such as current of power domains are measured); and col. 10 lines 27-49 and col. 11 line 64 to col. 12 line 6: (an amount of current (power budget) of each power domain that provide power is monitored and has a budget (such as 400mA); power is provided by the current distribution component to the components used by the circuit based on the power limits/budget of the power domain)].
Gupta does not teach wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source; one or more programmable registers configured to store a mapping between ones of the plurality of component circuits and ones of the at least two power sources, wherein the power splitter circuit is configured to: receive, from a particular one of the plurality of component circuits, a request for power credits to obtain power; access the mapping from the one or more programmable registers; determine, based on the mapping, which of the plurality of power sources supply power to the particular component circuit; and allocate, to the particular component circuit, a set of power credits from power budgets specific to the determined power sources. Gupta does not provide a stored mapping of power sources to components.
O’Conner teaches a plurality of power supplies that may provide power to specific computing components in a computing device through a power management component. O’Conner is thus similar to Gupta. O’Conner further teaches store a mapping between ones of the plurality of component circuits and ones of the at least two power sources [FIG. 2A, and 0039-0043: (power management engine 13 stores a power supply table 34 which lists processors that a particular power supply provides power to)], wherein the power splitter circuit is configured to: access the mapping from the one or more programmable registers [0043 and 0047-0049: (using the tables, loading capabilities of the power supplies are determined to see if additional power supplies are necessary; thus the tables are accessed)]; determine, based on the mapping, which of the plurality of power sources supply power to the particular component circuit [0039 and 0071: (examines the supply tables 28 and demand tables 30 to determine if additional power supplies are needed to power the processor)]; and allocate power to a given one of the plurality of component circuits based on one or more power budgets of one or more power sources mapped to the given component circuit as indicated by the mapping [0043 and 0047-0049: (after determination of adequate power, power is provided to processor 16c (component))]. O’Conner stores inside an engine, that controls connection of power supplies to processing components, a table that maps power supplies to processors, and then using such table to allocate power to the processors.
The combination of Gupta with O’Conner leads to Gupta’s current distribution component storing tables that map components to power domains, and selectively receiving power from power domains to provide power to the components based on such table.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use O’Conner’s teachings of a stored mapping of processor components to power supplies in Gupta. One of ordinary skill in the art would have been motivated to provide such a mapping in Gupta because it would allow the current distribution component to quickly determine which power domain/source can be provided to which processor components and to determine if additional power domains will be needed.
Gupta and O’Conner does not teach one or more programmable registers configured to store the mapping. O’Conner indicates that the table may be stored in the power management engine, but does not say that the storage in the power management engine is a register.
However, it is well known to one of ordinary skill in the art to use a register for storage of information for a processing element. Thus it would be obvious to one of ordinary skill in the art for Gupta and O’Conner to utilize a register for storing the power supply table within the power management engine (which is a processing element). One of ordinary skill in the art would have been motivated to use a register in Gupta and O’Conner because registers are fast, small, and easily accessed by the power management engine/processing element compared to other types of storages.
Gupta and O’Conner also do not teach wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source; receive, from a particular one of the plurality of component circuits, a request for power credits to obtain power; and allocate, to the particular component circuit, a set of power credits from power budgets specific to the determined power sources.
Piszczek teaches performing power management in a computing device with multiple power supplies. Piszczek is thus similar to Gupta and O’Conner. Piszczek further teaches wherein a given one of the plurality of power sources is associated with a power budget represented as one or more power credits usable to obtain power from the given power source [col. 12 lines 44-48, col. 13 lines 6-10, col. 13 lines 33-35: (power credits are allocated according to a power budget from power sources to computing devices)]; receive, from a particular one of the plurality of component circuits, a request for power credits to obtain power [col. 5 lines 19-24, col. 13 lines 27-30: (make request for more power credits)]; and allocate, to the particular component circuit, a set of power credits from power budgets specific to the determined power sources [col. 14 lines 5-14: (in response, provide extra power credit and col. 9 lines 48-53)]. Piszczek teaches representing power from power sources as power credits and providing excess power credits to other devices based on requests.
The combination of Gupta and O’Conner with Piszczek leads to the use of power credits and rate control circuits in Gupta and O’Conner’s power management engines or resource management engines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Piszczek’s teachings of power credits and rate control circuits in Gupta and. One of ordinary skill in the art would have been motivated to use power credits in Gupta and O’Conner because it allows for more efficient usage of power supplies based on loading levels since some loads may not need much power than others at a given time [Piszczek col 2 lines 50-56].
As per claim 19, Gupta, O’Conner, and Piszczek teach the medium of claim 18, wherein two of the plurality of power sources are configured to supply a different amount of power, and wherein a particular one of the plurality of component circuits is configured to receive power from the two power sources [Gupta col. 11 lines 23-25: (integrated circuit receives power from multiple power domains, and first power domain supplies more current than the second power domain)].
As per claim 20, Gupta, O’Conner, and Piszczek teach the medium of claim 18, wherein two of the plurality of power sources are configured to supply power to a particular one of the plurality of component circuits, and wherein the power splitter circuit is configured to: determine a first amount of power to supply the particular component circuit from a first one of the two power sources; and determine a second amount of power to supply the particular component circuit from a second one of the two power sources; select a minimum of the first amount of power and the second amount of power; and allocate the minimum amount of power to the particular component circuit [O’Conner 0073, 0076, and 0078: (checks each power supply and evaluate its efficiency at the current loading requirements, and only the power supply with the best matched is used; using the most efficient power supply for a given load means using the minimum amount of power to power a load)].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Conner et al. (hereinafter as O’Conner) PGPUB 2003/0056125, Piszczek et al. (hereinafter as Piszczek) USPAT 9,477,279, and Gupta et al. (hereinafter as Gupta) USPAT 11,079,824, and further in view of Chen et al. (hereinafter as Chen) PGPUB 2024/0120315.
As per claim 8, O’Conner, Piszczek, and Gupta teach the system of claim 7.
O’Conner, Piszczek, and Gupta do not teach wherein the first integrated circuit die and the second integrated circuit die are asymmetric with respect to each other.
Chen teaches a chip made of multiple dies. Chen is thus similar to O’Conner, Piszczek, and Gupta because they teach the use of multiple IC dies and providing power to them. Chen further teaches wherein the first integrated circuit die and the second integrated circuit die are asymmetric with respect to each other [0020: (a plurality of dies may be combined to form a larger chip such as heterogeneous chips having multiple die types)]. Chen teaches a heterogeneous chip made of different die types.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Chen’s teachings of heterogeneous chip having multiple different IC die types in O’Conner, Piszczek, and Gupta. One of ordinary skill in the art would have been motivated to have asymmetric dies in a heterogeneous chip in O’Conner, Piszczek, and Gupta because it would allow the chip to perform a greater variety of functions and provide flexibility.
Claim(s) 10-11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Conner et al. (hereinafter as O’Conner) PGPUB 2003/0056125, Piszczek et al. (hereinafter as Piszczek) USPAT 9,477,279, and Gupta et al. (hereinafter as Gupta) USPAT 11,079,824, and further in view of Keskin PGPUB 2024/0310888.
As per claim 10, O’Conner, Piszczek, and Gupta teach the system of claim 1.
O’Conner, Piszczek, and Gupta do not teach wherein a first one of the plurality of power sources is an electronic voltage regulator and a second one of the plurality of power sources is an inductor-based voltage regulator.
Keskin teaches a plurality of power sources providing power to a SoC and components within the SoC. Keskin is thus similar to O’Conner, Piszczek, and Gupta. Keskin further teaches wherein a first one of the plurality of power sources is an electronic voltage regulator [0032: (low dropout regulator, which uses a transistor)] and a second one of the plurality of power sources is an inductor-based voltage regulator [0032: (switching regulator, which uses inductors)].
The combination of O’Conner, Piszczek, and Gupta with Keskin leads to the power domains being different voltage regulator types that provide power to the current distribution component of each IC die, which powers respective components.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Keskin’s teachings of different types of voltage regulators to provide power to an IC chip in O’Conner, Piszczek, and Gupta. One of ordinary skill in the art would have been motivated to use different voltage regulator types in O’Conner, Piszczek, and Gupta because they provide redundancy and flexibility in switching between the regulators to obtain the more efficient power supply operation.
As per claim 11, O’Conner and Piszczek teach the system of claim 1.
O’Conner and Piszczek do not teach wherein at least one of the plurality of component circuits is a graphics processing unit (GPU). Although O’Conner mentions different processor types, O’Connor does not mention a GPU.
Keskin teaches a plurality of power sources providing power to a SoC and components within the SoC. Keskin is thus similar to O’Conner and Piszczek. Keskin further teaches wherein at least one of the plurality of component circuits is a graphics processing unit (GPU) [0033: (voltage regulators may supply a GPU)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Keskin’s teachings of the voltage regulators providing power to GPU in O’Conner and Piszczek. One of ordinary skill in the art would have been motivated to provide power to the GPU using the multiple power sources in O’Conner and Piszczek because it is a common system component that may use a significant amount of power in a computing device, and using multiple power sources to provide power to the GPU will improve its reliability.
As per claim 17, O’Conner and Piszczek teach the method of claim 12.
O’Conner and Piszczek do not teach wherein at least one of the multiple power sources is a battery.
Gupta teaches a current distribution component that receives power from multiple power domains and distributing the power to components. Gupta is thus similar to O’Conner and Piszczek. Gupta further teaches implementation onto a chip with multiple IC dies [col. 5 lines 30-33: (circuit may be a set of integrated circuits)].
The combination of O’Conner and Piszczek with Gupta leads to implementation of O’Conner’s teachings at an IC chip level where multiple power domains provide power to a current distribution component of an IC and the current distribution component utilizes its lookup tables to determine what components to provide power to, and using multiple IC chips.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Gupta’s teachings of multiple IC chips in which multiple power domains provide power to a current distribution component of each IC chip for distribution to components of the IC chip in O’Conner and Piszczek. Gupta teaches application of O’Conner and Piszczek’s teachings at an IC chip level. One of ordinary skill in the art would have been motivated to utilize Gupta’s teachings and implement O’Conner and Piszczek’s teachings at an IC chip level because it allows for efficient management of power sources at an IC chip level and would reduce waste in terms of power consumption.
O’Conner, Piszczek, and Gupta do not mention one of the multiple power sources is a battery. Gupta does power domain supplying DC voltage, but does not explicitly mention a battery.
Keskin teaches a plurality of power sources providing power to a SoC and components within the SoC. Keskin is thus similar to O’Conner, Piszczek, and Gupta. Keskin further teaches wherein one of the multiple power sources is a battery [FIG. 5 battery 530 and 0043: (battery may be used to supply power to SoC and the components in it)].
The combination of O’Conner, Piszczek, and Gupta with Keskin leads to using a battery as a power source in the power domain that supplies power to the chip with processor components.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Keskin’s teachings of using a battery to provide the DC power in O’Conner, Piszczek, and Gupta. One of ordinary skill in the art would have been motivated to use a battery as one of the power supplies in O’Conner, Piszczek, and Gupta because it allows for diversification of power supply sources to improve reliability.
Response to Arguments
Applicant's arguments filed 1/21/2026 have been fully considered but they are not persuasive. Applicant argues on pages 9-12 that neither O’Conner, Durham, or Gupta teach the amended limitations pertaining to power credits, and thus do not teach independent claims 1, 12, and 18 and their respective dependent claims. Examiner partially disagrees.
Examiner notes that although O’Conner, Durham, or Gupta do not mention power credits, the previous claims 9 and 15 did mention power credits and were rejected using either Rajwan or Piszczek. Applicant’s arguments did not mention the Rajwan or Piszczek references or explain why they would not teach the amended limitations. As a result, Examiner relied on the teachings of O’Conner in combination with Rajwan or Piszczek to address the amended independent claims.
For the reasons described above, the previously applied prior art still teach the amended claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANNY CHAN/Primary Examiner, Art Unit 2175