DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5 and 7-20 are pending.
Claims 1, 3, 7, 9-10, 12, 14, 16, and 18-20 have been amended.
This action is Non-Final.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-2, 7-10, 12-13, and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao PGPUB 2024/0085971, and further in view of Segawa et al. (hereinafter as Segawa) PGPUB 2015/0089261 and Becker USPAT 10,452,117.
As per claim 1, Cao teaches a system, comprising:
a plurality of component circuits [FIG. 1: core 1, core 2] implemented on a first integrated circuit die [FIG. 1: (implemented on package 104)];
a plurality of power sources, wherein a given one of the plurality of power sources is associated with a power budget [FIG. 1 0033, 0072, and 0087: (different voltage regulators (such as PMICs) are different power sources, and each has an associated current budget (power budget); for instance, voltage regulator in PMIC 120 is a first power source with a first current budget and voltage regulator in PMIC 124 is a second power source with a second current budget)]; and
a power splitter circuit coupled to the plurality of component circuits [0030, 0033, and 0074: (state-space unit (power splitter circuit) determines the budget for each PMIC (and its corresponding voltage regulator) and the state-space unit is connected to the PMICs)], wherein the power splitter circuit is configured to:
determine, a first set of the plurality of component circuits configured to receive power from a first one of the plurality of power sources [FIG. 1, 0032-0033, 0072, and 0087: (core 1 (first set of plurality of component circuits) is configured to receive a first amount of power from the voltage regulator of the first PMIC 120 (first one of the plurality of power sources) according to a first current power budget)] and a second set of plurality of component circuits configured to receive power from a second one of the plurality of power sources [FIG. 1, 0032-0033, 0072, and 0087: (core 2 (second set of plurality of component circuits) is configured to receive a second amount of power from the voltage regulator of the second PMIC 124 (second one of the plurality of power sources) according to a second current power budget)];
allocate, to the first set of component circuits, a first power budget associated with the first power source [0030, 0032-0033, 0072, 0074, and 0087: (first power budget associated with the voltage regulator of the first PMIC provided for the set of the first core)];
allocate, to the second set of component circuits, a second power budget associated with the second power source [0030, 0032-0033, 0072, 0074, and 0087: (second power budget associated with the voltage regulator of the second PMIC provided for the set of the second core)];
Cao does not explicitly teach the power budget represented as power credits usable to obtain power from the given power source; wherein the power splitter circuit includes one or more registers that are configured to store a mapping between ones of the plurality of component circuits and ones of the plurality of power sources. Cao teaches a plurality of power sources each with their own budget for providing power to respective loads, but Cao does not mention representing the budget as power credits or using a register to store a mapping between loads and the plurality of power sources.
Segawa teaches having a plurality of switching/voltage regulators (power sources) for providing power to different power-supply domains in a SoC device. Segawa is thus similar to Cao because they both teach multiple power sources delivering power to different components with an SoC. Segawa further teach wherein the power splitter circuit includes one or more registers that are configured to store a mapping between ones of the plurality of component circuits and ones of the plurality of power sources [FIG. 2 and 0124: (control register of PMIC sets the DC/DC converters of various power supply lines including the different domains of SoC; the control register can be referred to in order to identify which I/O device (and also power domain) is connected to which power-supply line (of a corresponding regulator)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Segawa’s teachings of a control register that identifies the loads for each regulator in Cao. Segawa’s teachings allows the state-space unit in Cao to have a control register that identifies which voltage regulator (of its PMIC) provides power to which component in the SoC. One of ordinary skill in the art would have been motivated to provide such a control register in Cao because it allows for quick enabling or disabling of power to loads, and thus allows for greater control and responsiveness.
Cao and Segawa do not teach the power budget represented as power credits usable to obtain power from the given power source, and allocating the power credits. Cao and Segawa do not appear to mention the use of power credits.
Becker teaches circuitry for delivering power to different subsystems of an integrated circuit. Becker is thus similar to Cao and Segawa. Becker further teaches the power budget represented as power credits usable to obtain power from the given power source [col. 1 lines 41-45, col. 5 lines 63-67: (power credits from budget)], and allocating the power credits [col. 4 lines 1-2, col. 8 lines 11-12: (allocate credits to the core loads)]. Becker shows a first portion of power credits from a first budget and a second portion of power credits from a second budget and allocating the power credits.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Becker’s teachings of using and allocating power credits to distribute the energy budget to different loads in Cao and Segawa. One of ordinary skill in the art would have been motivated to use credits in Cao and Segawa because it is a way to manage and quantify the amount of power provided to core loads, and allow for sharing of power credits to allow other devices to operate at higher power levels without needing to recalculate the budget.
As per claim 2, Cao, Segawa, and Becker teach the system of claim 1, wherein multiple power sources of the plurality of power sources are each configured to supply a respective, different amount of power [Cao 0024: (provide different power levels to each core)].
As per claim 7, Cao, Segawa, and Becker teach the system of claim 1, further comprising: a plurality of integrated circuit dies coupled together [Cao FIG. 1 SoC 106 and SoC 108], wherein the plurality of integrated circuit dies include: a first integrated circuit die comprising the plurality of component circuits and the power splitter circuit [Cao FIG. 1 SoC 106 and Becker FIG. 2: (a subsystem 202a has budget creating circuit (power splitter circuit)]; and a second integrated circuit die comprising another plurality of component circuits and another power splitter circuit [Cao FIG. 1 SoC 108 and Becker FIG. 2: (a subsystem 202n has budget creating circuit (power splitter circuit)].
As per claim 8, Cao, Segawa, and Becker teach the system of claim 7, wherein the first integrated circuit die and the second integrated circuit die are asymmetric with respect to each other [Cao FIG. 1 (SoCs 106 and 108 are not symmetrical in the picture)].
As per claim 9, Cao, Segawa, and Becker teach the system of claim 1, wherein a particular one of the plurality of component circuits includes a rate control circuit configured to manage power consumption in the particular component circuit based on a set of power credits [Cao FIG. 3: core throttle 304].
As per claim 10, Cao, Segawa, and Becker teach the system of claim 1, wherein a first one of the plurality of power sources is an electronic voltage regulator [Segawa 0050: (linear voltage regulator is an electronic regulator)] and a second one of the plurality of power sources is an inductor-based voltage regulator [Segawa 0050: (switching regulator is an inductor based regulator)].
Claim 12 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim 13 is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Claim 15 is similar in scope to claim 4 as addressed below and is thus rejected under the same rationale.
Claim 16 is similar in scope to claim 5 as addressed below and is thus rejected under the same rationale.
As per claim 17, Cao, Segawa, and Becker teach the method of claim 12, wherein at least one of the multiple power sources is a battery [Segawa 0049 and 0134].
Claim 18 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale. Cao further teach a plurality of integrated circuit dies coupled together [FIG. 1: (SoC 108 connected to SoC 106)].
As per claim 19, Cao, Segawa, and Becker teach the medium of claim 18, wherein two of the plurality of power sources are configured to supply a respective, different amount of power [Cao 0024: (provide different power levels to each core)], and wherein a particular one of the plurality of component circuits is configured to receive power from the two power sources [Cao 0024 and FIG. 1: (first processing core (one of the components) is configured to receive power from voltage regulator of PMIC 120 and second processing core is configured to receive power from voltage regulator of PMIC 124; this means the processor containing the first and second core receives power from the two power sources); additionally or alternatively, first processing core (one of the components) may also be considered to receive power from the two power sources (interpreted as receiving power from any of the power sources such as regulator from the PMIC 120 or regulator from the PMIC 124, because the language does not require receiving power from both of the power sources)].
Claim(s) 3-5, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao PGPUB 2024/0085971 in view of Segawa et al. (hereinafter as Segawa) PGPUB 2015/0089261 and Becker USPAT 10,452,117, and further in view of O’Conner et al. (hereinafter as O’Conner) PGPUB 2003/0056125
As per claim 3, Cao, Segawa, and Becker teach the system of claim 1, wherein the power splitter circuit is configured to: determine, based on the mapping, which of the plurality of power sources supply power to a particular one of the plurality of component circuits [Segawa 0124]; determine, based on power budgets specific to the determined power sources and a set of power split policies, a plurality of amounts of power suppliable by the determined power sources to a particular component circuit [Cao 0030, 0032-0033, 0072, 0074, and 0087].
Cao, Segawa, and Becker do not teach select a minimum of the plurality of amounts of power; and allocate the minimum amount of power to the particular component circuit via the set of power credits.
O’Conner teaches mapping a plurality of power sources to different loads of a computing device. O’Conner is thus similar to Cao, Segawa, and Becker. O’Conner further teaches select a minimum of the plurality of amounts of power; and allocate the minimum amount of power to the particular component circuit via the set of power credits [O’Conner 0073, 0076, and 0078: (checks each power supply and evaluate its efficiency at the current loading requirements, and only the power supply with the best matched is used; using the most efficient power supply for a given load means using the minimum amount of power to power a load)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use O’Conner’s teachings of selecting the power source that will use the least amount of power and allocating it to the load in Cao, Segawa, and Becker. One of ordinary skill in the art would have been motivated to use O’Conner’s teachings of having multiple power sources or regulators provide power to the same load in Cao, Segawa, and Becker because it improves reliability by having redundant power sources to components. One of ordinary skill in the art would further be motivated to select the power source that will have the smallest power consumed to provide power to a load in Cao, Segawa, and Becker because it improves efficiency.
As per claim 4, Cao, Segawa, Becker, and O’Conner teach the system of claim 3, wherein the power splitter circuit is configured to reallocate, from at least one of the multiple power sources, an unused portion of power to a corresponding power budget in a next power allocation cycle [Becker col. 8 lines 49-56 and col. 10 lines 30-31: (power credits are allocated (in first allocation cycle), and then in response to indications of unused energy credits, unused credit are provided to a credit sharing unit to share the unused credit (next cycle)].
As per claim 5, Cao, Segawa, Becker, and O’Conner teach the system of claim 3, wherein the power splitter circuit is configured to apply a same power split policy to the respective power budgets of the determined power sources [Becker col. 6 lines 55-56: (watt hours distributed evenly)].
Claim 14 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
As per claim 20, Cao, Segawa, and Becker teach the medium of claim 19, wherein two of the plurality of power sources are configured to supply power to a particular one of the plurality of component circuits, and wherein the power splitter circuit is configured to: determine a first amount of power to supply the particular component circuit from a first one of the two power sources [Segawa 0124 and Cao 0032-0033: (power provided from a power source to a load)]; and determine a second amount of power to supply the particular component circuit from a second one of the two power sources [Segawa 0124 and Cao 0032-0033: (power provided from a power source to another load)].
Cao, Segawa, and Becker do not teach select a minimum of the first amount of power and the second amount of power; and allocate the minimum amount of power to the particular component circuit.
O’Conner teaches mapping a plurality of power sources to different loads of a computing device. O’Conner is thus similar to Cao, Segawa, and Becker. O’Conner further teaches select a minimum of the first amount of power and the second amount of power; and allocate the minimum amount of power to the particular component circuit [O’Conner 0073, 0076, and 0078: (checks each power supply and evaluate its efficiency at the current loading requirements, and only the power supply with the best matched is used; using the most efficient power supply for a given load means using the minimum amount of power to power a load)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use O’Conner’s teachings of selecting the power source that will use the least amount of power and allocating it to the load in Cao, Segawa, and Becker. One of ordinary skill in the art would have been motivated to use O’Conner’s teachings of having multiple power sources or regulators provide power to the same load in Cao, Segawa, and Becker because it improves reliability by having redundant power sources to components. One of ordinary skill in the art would further be motivated to select the power source that will have the smallest power consumed to provide power to a load in Cao, Segawa, and Becker because it improves efficiency.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao PGPUB 2024/0085971 in view of Segawa et al. (hereinafter as Segawa) PGPUB 2015/0089261 and Becker USPAT 10,452,117, and further in view of Keskin PGPUB 2024/0310888.
As per claim 11, Cao, Segawa, and Becker teach the system of claim 1.
Cao, Segawa, and Becker do not teach wherein at least one of the plurality of component circuits is a graphics processing unit (GPU).
Keskin teaches a plurality of power sources providing power to a SoC and components within the SoC, and the use of different types of regulators. Keskin is thus similar to Cao, Segawa, and Becker. Keskin further teaches wherein at least one of the plurality of component circuits is a graphics processing unit (GPU) [0033: (voltage regulators may supply a GPU)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Keskin’s teachings of the voltage regulators providing power to GPU in Cao, Segawa, and Becker. One of ordinary skill in the art would have been motivated to provide power to the GPU using the multiple power sources in Cao, Segawa, and Becker because it is a common system component that may use a significant amount of power in a computing device, and using multiple power sources to provide power to the GPU will improve its reliability.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Koorapati et al. (PGPUB 2024/0428024) teaches a table assigning power rails by respective PMICs to devices in processor based system.
Humphrey et al. (PGPUB 2019/0073013) teaches mapping the system of power supplies and computing device.
Erad et al. (PGPUB 2017/0060226) teaches showing a map associating power supplier supplies to each power consumption module in a computing device [0038].
Fujita (PGPUB 2013/0104131) teaches an assignment table that shows an on/off state of power source of an assignment destination processing device [0027].
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/DANNY CHAN/Primary Examiner, Art Unit 2175
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