DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/21/2023 and 06/04/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations stated in claim 10 must be shown or the feature(s) canceled from the claim(s). It’s unclear which figure, if any, shows that the first field plate bias circuit includes an output capacitance coupled between the first source finger and the first field plate finger. No new matter should be entered.
The drawings are also objected to because par. 33 mentions electrode 252 in fig. 2, however there is no 252 in this figure.
Par. 37, 39, and 40 mention gate fingers 325 and field plate fingers 327, however, in fig. 3, the gate fingers are shown to be 327 and the field plate fingers are shown to be 325.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 2-14 are objected to because of the following informalities:
For the preamble of claims 2-14, “the device” should read “the electronic device” in order to align with claim 1.
Claim 13, line 2: “voltage regulation circuitry is configured to…” should read “voltage regulation circuitry that is configured to…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-6 and 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, it says that “the field plate bias circuitry is coupled between the second current terminal and the output node,” however the second current terminal is 122 in fig. 1, which is connected to ground. The claim is unclear and indefinite. Examiner interprets this limitation to mean coupled between the first current terminal 124 and the output node. Appropriate correction is required. Claims 4-6, which are dependent on claim 3, inherit this rejection.
Claim 12 recites the limitation "the output node of the field plate bias circuitry" in lines 5-6. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required. Claims 13-14, which are dependent on claim 12, inherit this rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 12, and 15 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20140203877 by Ota.
Regarding claim 1, Ota teaches an electronic device (Fig. 1, 3, 6, 8), comprising:
an input node (RFin) and an output node (RFout);
a transistor (50, 50a) comprising:
a first current terminal (103) coupled to the output node (RFout);
a second current terminal (102);
a semiconductive channel region (Fig. 2 100, par. 38) disposed between the first current terminal and the second current terminal;
a gate electrode (105) electrically coupled to the semiconductive channel region and coupled to the input node (RFin);
a field plate electrode (106) electrically coupled to the semiconductive channel region and disposed adjacent to the gate electrode (105); and
field-plate bias circuity (110, 110a, 110b, 117 and 116) coupled to the field plate electrode (106) and configured to apply a desired field plate bias voltage to the field plate electrode that at least partially depletes the channel region of charge carriers near the field plate electrode.
Regarding claim 2, Ota teaches the device of claim 1 wherein the field plate electrode (106) is disposed between the gate electrode (105) and the first current terminal (103).
Regarding claim 3, Ota teaches the device of claim 1, wherein the field plate bias circuitry (110, 110a, 110b, 117 and 116) is coupled between the second current terminal (103; examiner interprets this to mean first current terminal) and the output node (RFout);
wherein the field plate bias circuitry is configured to generate the field plate bias voltage to the field plate electrode in response to a time-varying voltage at the output node (Par. 38, 84).
Regarding claim 5, Ota teaches the device of claim 3, wherein the transistor and at least part of the field plate bias circuitry are integrally formed within semiconducting material of a single semiconductor substrate (Par. 82; Fig. 8).
Regarding claim 12, Ota teaches the device of claim 1, wherein field plate bias circuitry (Fig. 13 182a and 184a) comprises:
an input capacitance (184a) and an output capacitance (182a);
wherein the input capacitance is coupled between the first current terminal (13) and the output capacitance (182a);
wherein the output capacitance (182a) is coupled between the output node of the field plate bias circuitry (output of 182a is connected to field plate electrode 17a) and a reference potential node (ground 19).
Regarding claim 15, Ota teaches an amplifier device (Fig. 1, 3, 6, 8) comprising:
an input node (RFin) configured to receive a radiofrequency (RF) input signal;
an output node (RFout) configured to output an amplified signal corresponding to the RF input signal;
a transistor (50, 50a) configured to amplify the RF input signal, wherein the transistor comprises:
a first current terminal (103);
a second current terminal (102);
a semiconductive channel (Fig. 2 100, par. 38) coupled between the first current terminal and the second current terminal;
a gate electrode (105) disposed between the first current terminal (103) and the second current terminal (102) and coupled to the semiconductive channel (Fig. 2 100, par. 38) and configured to modulate an output of the transistor in response to the RF input signal; and
a field plate electrode (106) that is adjacent to the gate electrode (105) and also coupled to the semiconductive channel; and
field-plate bias circuity (110, 110a, 110b, 117 and 116) coupled to the field plate electrode (106) and configured to apply a desired field plate bias voltage to the field plate electrode that at least partially depletes the channel region of charge carriers near the field plate electrode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ota as applied to claim 1 above, and further in view of US 9520480 by Bhalla et al.
Regarding claim 11, Ota teaches the device of claim 1, but fails to teach that the transistor is a high electron mobility transistor (HEMT) and the channel region comprises a semiconductor heterostructure configured to form a two-dimensional electron gas (2DEG) at a buried semiconductor heterojunction within the semiconductor heterostructure.
However, different transistor types such as HEMTs are well known in the art, as shown in US 9520480 by Bhalla et al. and are used to reduce on-resistance and realize higher breakdown voltage (Col. 1 lines 33-47). Bhalla also teaches a 2DEG layer (Fig. 1; Fig. 2 115) within the semiconductor heterostructure.
It would be obvious to combine the teachings of the transistor structure of Bhalla with the electronic device in Ota in order to reduce on-resistance, realize higher breakdown voltage, and have a 2DEG layer which can form uninterrupted between the source and drain electrodes of the transistor and thus turn on the device, even if there’s no control voltage applied to the gate (Col. 1 lines 50-54; Col. 1 lines 66-67 - Col. 2 lines 1-3; Col. 5 lines 17-19).
Allowable Subject Matter
Claims 7-10 and 16-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4, 6, and 13-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren-Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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