DETAILED ACTION
Claims 21 – 40 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21,25-31,34-38 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated Morrow (US Publication 20080046702 A1).
Regarding claim 21, Morrow discloses a computer-implemented method comprising:
performing successive calls to a time function that is instantiated on a computing device including an initial call followed by a subsequent call [branch instruction call followed by next time call], the time function interfacing with a continuously running counter associated with a processor on the computing device to retrieve a current value of the continuously running counter, the processor including a processor pipeline and a data cache [0032: I-cache 230 after the indirect branch instruction associated with indirect branch instruction address 256 and its corresponding target address (0x2000) are stored in I-cache 230 at address 0x000B. Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000] [0032-0038];
in response to the initial call to the time function, loading instructions associated with the time function in the processor pipeline and caching data associated with the time function in the data cache [0032: I-cache 230 after the indirect branch instruction associated with indirect branch instruction address 256 and its corresponding target address (0x2000) are stored in I-cache 230 at address 0x000B. Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000] [0032-0038];
executing the instructions in the pipeline using the data in the data cache to initially return the current value of the continuously running counter to the time function [0032-0038] [0037: If it is, the method 400 proceeds to block 440 where the branch target address is sent to the program counter such as instruction prefetch unit 128 in order for instructions to begin being fetched from the branch target address]; and
in response to the subsequent call to the time function, re-executing the instructions in the pipeline and reusing the data in the data cache to subsequently return the current value of the continuously running counter to the time function [0032: Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000][0035-0038][0041-0042].
Regarding claim 25, Morrow discloses the computer-implemented method of claim 21 in which the processor applies predictive execution to optimize execution of the instructions in response to the initial call and uses results of the predictive execution for re-execution of the instructions in response to the subsequent call [0032-0042].
Regarding claim 26, Morrow discloses the computer-implemented method of claim 21 in which the processor pipeline is configured with stages comprising fetching, decoding, execution, and writing-back [0032-0042].
Regarding claim 27, Morrow discloses the computer-implemented method of claim 26 in which the processor pipeline is configured with predictive execution capabilities [0032-0042, figure 4].
Regarding claim 28, Morrow discloses the computer-implemented method of claim 26 in which the processor comprises a multi-level instruction caches or multiple cores, wherein each of the multiple cores includes an individual continuously running counter, or the multiple cores commonly share a continuously running counter [0027-0038].
Regarding claim 29, Morrow discloses a hardware-based computer-readable memory device storing computer-executable instructions which, upon execution by a processor in a computing device, cause the computing device to: operate a continuously running counter instantiated as a hardware register in the processor, the continuously running counter running at an invariant rate; operate a pipeline on the processor; operate a data cache on the processor [0032: I-cache 230 after the indirect branch instruction associated with indirect branch instruction address 256 and its corresponding target address (0x2000) are stored in I-cache 230 at address 0x000B. Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000] [0032-0038];
place an initial call to a time function interfacing with the continuously running counter; prime the pipeline by loading time function instructions into the pipeline in response to the initial call; prime the data cache by storing data associated with the time function in the data cache in response to the initial call [0032: I-cache 230 after the indirect branch instruction associated with indirect branch instruction address 256 and its corresponding target address (0x2000) are stored in I-cache 230 at address 0x000B. Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000] [0032-0038];
place a subsequent call to the time function in which the processor remains in a working state without transitioning to a sleep state when executing the time function from the subsequent call based on the pipeline and data cache each being respectively primed responsively to the initial call to the time function; and in response to execution of the time function from the subsequent call, obtain a value from the continuously running counter on the processor while the processor remains in the working state [0032: Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000][0035-0038][0041-0042].
Regarding claim 30, Morrow discloses the hardware-based computer-readable memory device of claim 29 in which the initial and subsequent calls to the time function are implemented by an application feature [0032-0042].
Regarding claim 31, Morrow discloses the hardware-based computer-readable memory device of claim 29 in which the initial and subsequent calls to the time function are implemented by an operating system feature [0032-0042].
Regarding claim 34, Morrow discloses a computing device, comprising:
a processor; a data cache; and
a hardware-based computer-readable storage medium having computer-executable instructions stored thereon which, when executed by the processor, cause the computing device to: operate a continuously running counter instantiated as a hardware register in the processor, the continuously running counter running at an invariant rate; operate a pipeline in the processor; perform multiple calls to a time function that is instantiated on the computing device including an initial call followed by a subsequent call, the time function interfacing with the continuously running counter to retrieve current values of the continuously running counter [0032: I-cache 230 after the indirect branch instruction associated with indirect branch instruction address 256 and its corresponding target address (0x2000) are stored in I-cache 230 at address 0x000B. Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000] [0032-0038];
in response to the initial call to the time function, prime the data cache with data; execute the instructions in the pipeline using the data from the primed cache to initially return the current value of the continuously running counter to the time function [0032: I-cache 230 after the indirect branch instruction associated with indirect branch instruction address 256 and its corresponding target address (0x2000) are stored in I-cache 230 at address 0x000B. Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000] [0032-0038]; and
in response to the subsequent call to the time function, reuse data from the primed cache to subsequently return the current value of the continuously running counter to the time function [0032: Consequently, the next time the processor's program counter points to address 0x000B, an I-cache lookup will hit and the target address 0x2000 will be assigned to the processor's program counter to begin redirecting the pipeline 112 with instructions at address 0x2000][0035-0038][0041-0042].
Regarding claim 35, Morrow discloses the computing device of claim 34 in which the instructions further cause the computing device to load instructions associated with the time function in the pipeline [0032-0042].
Regarding claim 36, Morrow discloses the computing device of claim 35 in which the instructions further cause the computing device to re-execute the instructions in the pipeline [0032-0042].
Regarding claim 37, Morrow discloses the computing device of claim 34 in which the instructions further cause the computing device to expose an application programming interface (API) to enable the multiple calls to be invoked from one or more applications that are operative on the computing device [0032-0042].
Regarding claim 38, Morrow discloses the computing device of claim 34 in which the multiple calls to the time function are placed from an application that is operative on the computing device and the time function is instantiated as an operating system function [0032-0042].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24,39 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow (US Publication 20080046702 A1) and in view of Chynoweth et al (US Publication 20190041950 A1).
Regarding claim 24, Morrow discloses the successive calls to the time function cause the processor to remain in a working state while re-executing the instructions and reusing the cached data to subsequently return the current value of the continuously running counter to the time function [0032-0042]. However, Morrow does not explicitly disclose the processor has a working state and a sleep state. Chynoweth discloses the processor is configured to switch between working and sleep states in which the working state comprises a normal operating mode, and the sleep states comprise one or more energy-conserving C-modes [0023-0025: processor power modes].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Morrow and Chynoweth together because they both directed to use cache to execute subsequent instruction. Chynoweth’s disclosing of the power states of the processor would allow Morrow to save more power consumption by enabling the processor to enter one of the low power modes based on the instructions.
Regarding claim 39, Morrow does not explicitly teach the processor is configured to switch between working and sleep states in which the working state comprises a normal operating mode, and the sleep states comprise one or more energy-conserving C-modes.
Chynoweth discloses the processor is configured to switch between working and sleep states in which the working state comprises a normal operating mode, and the sleep states comprise one or more energy-conserving C-modes [0023-0025: processor power modes].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Morrow and Chynoweth together for the same rationale disclosed in claim 24 above.
Regarding claim 40, Chynoweth discloses the computing device of claim 39 in which remaining in the working state comprises not entering a sleep state [0023-0025].
Allowable Subject Matter
Claims 22-23,32-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record do not disclose nor suggest the limitation disclosed in claims 22-23,32-33.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176