DETAILED ACTION Non-Final Rejection Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Shimizu et al. (US 2004/0175850) . Regarding Claim 1 . Shimizu teaches a n apparatus comprising ( fig. 3) : a first platform including a wafer interface configured ( 6: fig.1; 12-15: fig.3 ) to engage, on a silicon wafer ( W : fig. 1; TIC: fig.3; [0064]) , contacts for a selected processing device ( W: fig.1; semiconductor device: fig.3) of a plurality of processing devices incorporated in the silicon wafer ( a program and tests each of designed semiconductor chips, on a wafe r on which the designed semiconductor chips are formed, together with the semiconductor chips, supplying a source voltage to at least the test circuit module from the outside to thereby test each semiconductor chip on the same wafer by the test circuit module, and selecting the semiconductor chip judged to be non-defective, as a product :[0022] ) ; and a second platform (4: fig.1) including at least a portion of an emulator system operatively coupled (tester T: fig.3;) to the wafer interface ( 12- 1 5: fig. 3 ) to electrically engage the contacts for the selected processing device( semiconductor device(chip): fig.3 ), the emulator system configured (Tester T: fig. 3 ) to model a computing device (16: fig. 3) in which the selected processing device is to be used ( semiconductor device: fig.3 ) , the emulator system including components (12-15) configured to enable the selected processing device to participate in execution of software via the emulator system to test functionality of the selected processing device (the functions of the semiconductor integrated circuit device TIC to be tested, in HDL and simulating and verifying its HDL descriptive text by a hardware emulator:[0062]-[0065]) . . Regarding Claim 2 . Shimizu further teaches the wafer interface comprises a multi-layer organic (MLO) package configured to provide electrical connections between bumps disposed on the silicon wafer that correspond to the contacts and the emulator system ( 5: fig.2; [0058] - [ 0060]) . Regarding Claim 3 . Shimizu further teaches the components of the emulator system that are disposed on the second platform include at least one of: a power supply coupling ( 12: fig.3) ; a Joint Test Action Group (JTAG) interface ( 14-15: fig.3) ; a universal serial bus (USB) interface ( FPGA: [0058], [0078]) ; a nonvolatile memory express ( NVMe ) interface ( FPGA: [0058], [0078]) ; a universal flash storage (UFS) interface ( FPGA: [0058], [0078]) ; a secure digital (SD) interface ( FPGA: [0058], [0078]) ; or a power management integrated circuit (PMIC ) ( 13: fig. 3; [0063]) . Regarding Claim 4 . Shimizu further teaches the components of the emulator system include at least one dynamic random-access memory (DRAM) device ( FPGA: [0058], [0078]) . Regarding Claim 5 . Shimizu further teaches the at least one dynamic random-access memory (DRAM) device of the emulator system is part of the first platform ( FPGA: [0058], [0078]) . Regarding Claim 6 . Shimizu further teaches the at least one DRAM device of the emulator system is disposed on the wafer interface ( FPGA: [0058], [0078]) . Regarding Claim 7 . Shimizu further teaches the wafer interface includes a first side and a second side that is opposite the first side ( 2: fig.1) ; the first side ( 6: fig.1) faces the selected processing device ( W : fig.1) ; the second side ( 4: fig.1) faces the first platform ( 3: fig.1) ; and the at least one DRAM device is disposed on the second side of the wafer interface ( 5: fig.1) . Regarding Claim 8 . Shimizu further teaches the components of the emulator system include at least one capacitor ( stray capacitance: [0102]) ; and the first platform comprises the at least one capacitor of the emulator system ( [0102]) . Regarding Claim 9 . Shimizu further teaches the emulator system is configured to test the functionality of the selected processing device in participating in the execution of the software while the selected processing device remains part of the silicon wafer ( Test program: fig. 3;[ 0063], [0069], [0080]) . Regarding Claim 10 . Shimizu further teaches the components of the emulator system include a first set of one or more components (12-15: fig. 3) and a second set of one or more components ( 5: fig.1) ; the first set of one or more components (12-15: fig. 3) is disposed on the first platform ( Tester T: fig.3) ; and the second set of one or more components ( 5: fig.1) is disposed on the second platform ( TIC: fig.3) . Regarding Claim 11 . Shimizu further teaches the first set of one or more components comprise at least one of a dynamic random-access memory (DRAM) device or a decoupling capacitor (FPGA: [0058], [0078]) . Regarding Claim 12 . Shimizu further teaches the emulator system is configured to provide higher memory bandwidth to the selected processing device due to placement of the DRAM device at the first platform being relatively closer to the selected processing device as compared to the second platform (FPGA: [0058] -[ 0060] , [0078]) . Regarding Claim 13 . Shimizu teaches A system comprising (fig.1) : automatic test equipment (WS: fig. 1) configured to support a silicon wafer (W: fig. 1) and to position one or more probe cards to electrically couple to the silicon wafer ( 6: fig.1) ; and a probe card of the one or more probe cards including ( 2: fig.1) : a first platform including a wafer interface configured to engage (6: fig.1) , on the silicon wafer (W: fig.1) , contacts for a selected processing device of a plurality of processing devices incorporated in the silicon wafer (TIC: fig. 3 ; (a program and tests each of designed semiconductor chips, on a wafe r on which the designed semiconductor chips are formed, together with the semiconductor chips, supplying a source voltage to at least the test circuit module from the outside to thereby test each semiconductor chip on the same wafer by the test circuit module, and selecting the semiconductor chip judged to be non-defective, as a product:[0022]) ; and a second platform (4: fig.1) including at least a portion of an emulator system operatively coupled to the wafer interface (3: fig.1; Tester T: fig. 3) to electrically engage the contacts for the selected processing device (12-15: fig. 3) , the emulator system configured (Tester T: fig. 3) to model a computing device (16: fig. 3) in which the selected processing device is to be used semiconductor device: fig.3) , the emulator system including components configured (12-15) to enable the selected processing device to participate in execution of software via the emulator system to test functionality of the selected processing device (the functions of the semiconductor integrated circuit device TIC to be tested, in HDL and simulating and verifying its HDL descriptive text by a hardware emulator:[0062]-[0065]) . Regarding Claim 14 . Shimizu further teaches the first platform ( 6: fig.1) is positioned between the second platform (4: fig.1) and the selected processing device during testing of the selected processing device ( W: fig.1; [0022]) ; and the automatic test equipment (3: fig. 1; Tester T: fig.3) is configured to physically connect the wafer interface with a surface of the silicon wafer during testing of the selected processing device ( 6: fig.1; 12-15: fig.3) . Regarding Claim 15 . Shimizu further teaches the components of the emulator system include a first set of one or more components (12-15: fig.3) and a second set of one or more components ( 5: fig.1) ; the first set of one or more components is disposed on the first platform (6: fig. 1; 12-15: fig.3) ; and the second set of one or more components is disposed on the second platform ( 5: fig.1) . Regarding Claim 16 . Shimizu further teaches the automatic test equipment includes a plurality of probe cards including the probe card ( 2b: fig.16; [0135] - [ 0136]) , each respective probe card of the plurality of probe cards including ( 2: fig.1; 2b: fig.16) : a respective first platform ( 6: fig.1) having a respective wafer interface ( W: fig.1) ; and a respective second platform (4: fig. 1) having at least a portion of a respective emulator system ( 3: fig.1; Tester T: fig. 3) ; and the automatic test equipment is configured to substantially simultaneously test multiple processing devices of the plurality of processing devices incorporated in the silicon wafer using the plurality of probe cards ([0115], [0135] -[ 0136]) . Regarding Claim 17 . Shimizu further teaches the first platform includes at least one dynamic random-access memory (DRAM) device disposed on the wafer interface ( FPGA: [0058], [0078]) ; and the wafer interface is configured to electrically couple the DRAM device to the selected processing device to enable the selected processing device to participate in the execution of the software via the emulator system ( Test program: fig. 3;[ 0063], [0069], [0080]) . Regarding Claim 18 . Shimizu teaches a method comprising ( [0011] -[ [0014]]) : deploying a wafer interface of a first platform to a surface of a silicon wafer (6: fig.1; 12-15: fig.3) to engage contacts for a selected processing device (W: fig. 1; TIC: fig.3; [0064]) of a plurality of processing devices incorporated in the silicon wafer (a program and tests each of designed semiconductor chips, on a wafe r on which the designed semiconductor chips are formed, together with the semiconductor chips, supplying a source voltage to at least the test circuit module from the outside to thereby test each semiconductor chip on the same wafer by the test circuit module, and selecting the semiconductor chip judged to be non-defective, as a product:[0022]) ; operatively coupling an emulator system (tester T: fig.3;) having one or more components that are supported (12-15: fig. 3) by a second platform (4: fig.1) to the wafer interface to electrically engage the contacts for the selected processing device (12-15: fig.1) , the emulator system (tester T: fig.3) configured to model a computing device (16: fig. 3) in which the selected processing device is to be used (semiconductor device: fig.3) ; operating the selected processing device by executing software using the selected processing device and the one or more components of the emulator system ( the functions of the semiconductor integrated circuit device TIC to be tested, in HDL and simulating and verifying its HDL descriptive text by a hardware emulator: [ 0062] -[ 0065]) ; and monitoring results of the executing of the software to evaluate functionality of the selected processing device with respect to the software ( inputting a test pattern and observing an output is performed: [0062] -[ 0065]; [0108]) . Regarding Claim 19 . Shimizu further teaches employing, by automatic test equipment (ATE), the emulator system and the wafer interface as a probe card (test t: fig.3; 2: fig.1) to test software execution with the selected processing device prior to separation of the selected processing device from others of the plurality of processing devices incorporated in the silicon wafer ( Test program: fig. 3; [ 0063], [0069], [0080]) . Regarding Claim 20 . Shimizu further teaches the operating comprises: operating the selected processing device by executing the software using the selected processing device, the one or more components of the emulator system, and at least one other component of the emulator system that is supported by the first platform ( [0062] -[ 0065], [0069], [0080]) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. a) Sommers (US 2024/0069099) : receiving test configuration information associated with a test session for configuring a test infrastructure, wherein the test infrastructure includes a switching fabric emulator comprising at least one switching application-specific integrated circuit (ASIC) or programmable switching chip. b) Wang Et al. (US 8957691): A device includes a probe card, which further includes a chip. The chip includes a semiconductor substrate, a test engine disposed in the chip, wherein the test engine comprises a device formed on the semiconductor substrate, wherein the device is selected from the group consisting essentially of a passive device, an active device, and combinations thereof. A plurality of probe contacts is formed on a surface of the chip and electrically connected to the test engine. c) Akram et a. (US 6.246,245): A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. d) Fu. et al. (US 2007/0216429): A probe card has a plurality of probe needle groups arranged in a predetermined pattern. The predetermined pattern is obtained by assuming a plurality of unit regions 11-14 arranged adjacent to each other to form a chip group region. e) Nulty et al. (US 6,847,218): an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example. f) Nulty et al. (US 7,112,975): an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of holes may extend through the SOI layer and the plurality of probe dice, with each hole corresponding to a pad on a probe die. The anti-wafer structure may be advantageously used in an advanced probe card. Techniques for fabricating an anti-wafer and an advanced probe card are also disclosed. Contact information Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MOHAMMAD K ISLAM whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0328 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9:00 a.m. - 5:00 p.m. . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD K ISLAM/ Primary Examiner, Art Unit 2857