Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed 03/24/2026.
Claims 1-7, 8-14, 15-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7, 8-14, 15-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 11, 13, 15, 18, 20, 1, 4, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. ( US 20230164725, hereinafter, Wang’s 725 ) in view of YAMAGATA ( US 20240255898, hereinafter, YAMAGATA’s 898.
Regarding to the claim 8, US 20230164725 teaches a system comprising:
a processor; and
a memory storing machine-readable instructions that, when executed by the processor, cause the processor to:
synchronize a plurality of remote interface units (master device , slave device ) [see Figures 3-4 ] to a network time, the plurality of RIUs ( master device, slave device ) being connected in a network [see Figures 3-4 and Paragraphs 0025-0026 ];
receiving, by a first ( slave device ) [see Figures 3-4 and Paragraphs 0025-0026 ] of the plurality of RIUs ( master device , slave device ) , a one pulse-per-second (1PPS) signal;
determine a 1PPS receive time (determining the receiving the synchronization signal frame from the master device during first period ) [see Figure 3] ( 413 , receive time) [see Figure 4 ] and a 1PPS period (T1 period ) [see Figure 4 ]based on the 1PPS signal and with respect to the single network time, the 1PPS receive time being when the 1PPS signal is received by the first (slave device ) of the plurality RIUs [see Figures 3-4 and Paragraphs 0025-0026 ]
( [0009] The disclosure further provides a master device including a processing circuit and a compensation estimation circuit. The processing circuit is configured to transmit a synchronization signal frame to a slave device during a first period of an i.sup.th second. The synchronization signal frame includes a synchronization header, a first pulse per second (1PPS) signal, first time of date information, and first phase compensation information. The first phase compensation information is configured to request the slave device to correct a transmission time point at which a first reference 1PPS signal is transmitted during a second period of the i.sup.th second. The compensation estimation circuit is coupled to the processing circuit and is configured for receiving the first reference 1PPS signal from the slave device during the second period of the i.sup.th second and determining second phase compensation information transmitted to the slave device according to a receiving time point at which the first reference 1PPS signal is received during a first period of an (i+1).sup.th second ) .
However, US 20230164725 does not explicitly teach transmit, by the first of the plurality of RIU, a message to a second of the plurality of RIUs.
US 20240255898, from the same or similar fields of endeavor, teaches synchronize a plurality of remote interface units ( Grand Master Clock 100, node 10A, node 40 ) [see Figure 7] to a single network time, the plurality of RIUs being connected in a network [see Paragraphs 0101 – 0106];
Receive, by a first (node 10A) of the plurality of RIUs, a one pulse per second (1pps) signal [see Paragraph 0096];
Transmit, by the first (node 10A ) of the plurality of RIUs , a message (PTP packet) to a second ( node 40 ) of the plurality of RIUs , the message (PTP) including the 1pps receive time and 1pps period, and the second (40) [see Figure 7] of the plurality of RIUs being one of the plurality of RIUs other than the first (10A) of the plurality of RIUs [see Paragraphs 0096 & 0101-0106].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the system of US 20230164725 in view of US 20240255898 because US 20240255898 suggests that an object of the present disclosure made in view of the above-described problems is to provide a measurement instrument, a measurement method, and a time synchronization system capable of relaxing the above-described constraints and measuring the accuracy of the in-device time more simply.
Regarding to the claim 11, US 20230164725 and US 20240255898 teach the limitations of the claim 8 above.
However, US 20230164725 does not explicitly teach wherein the single network time is based on at least one of:precision time protocol (PTP); or generic precision time protocol (gPTP).
US 20240255898, from the same or similar fields of endeavor, teaches wherein the single network time is based on at least one of: precision time protocol (PTP) (wherein the single network time is based on precision time protocol (PTP) [see Figure 7 and Paragraphs 0096 & 0101-0106 ] ; or generic precision time protocol (gPTP).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the system of US 20230164725 in view of US 20240255898 because US 20240255898 suggests that an object of the present disclosure made in view of the above-described problems is to provide a measurement instrument, a measurement method, and a time synchronization system capable of relaxing the above-described constraints and measuring the accuracy of the in-device time more simply.
Regarding to the claim 13, US 20230164725 further teaches receive, by the first of the plurality of RIUs, a 10MHz frequency reference; and determine the 1PPS receive time and the 1PPS period based on the 1PPS signal and the 10MHz frequency reference and with respect to the single network time (receive, by the first of the plurality of RIUs, a 10MHz frequency reference; and determine the 1PPS receive time and the 1PPS period based on the 1PPS signal and the 10MHz frequency reference and with respect to the single network time) [see Figures 3-4 and Paragraphs 0025-0026 & 0029 & 0037].
Regarding to the claim 15, US 20230164725 teaches a non-transitory computer-readable medium including instructions that when executed by a processor cause the processor to:
synchronize a plurality of remote interface units (master device , slave device ) [see Figures 3-4 ] to a network time, the plurality of RIUs ( master device, slave device ) being connected in a network [see Figures 3-4 and Paragraphs 0025-0026 ];
receiving, by a first ( slave device ) [see Figures 3-4 and Paragraphs 0025-0026 ] of the plurality of RIUs ( master device , slave device ) , a one pulse-per-second (1PPS) signal;
determine a 1PPS receive time (determining the receiving the synchronization signal frame from the master device during first period ) [see Figure 3] ( 413 , receive time) [see Figure 4 ] and a 1PPS period (T1 period ) [see Figure 4 ]based on the 1PPS signal and with respect to the single network time, the 1PPS receive time being when the 1PPS signal is received by the first (slave device ) of the plurality RIUs [see Figures 3-4 and Paragraphs 0025-0026 ]
( [0009] The disclosure further provides a master device including a processing circuit and a compensation estimation circuit. The processing circuit is configured to transmit a synchronization signal frame to a slave device during a first period of an i.sup.th second. The synchronization signal frame includes a synchronization header, a first pulse per second (1PPS) signal, first time of date information, and first phase compensation information. The first phase compensation information is configured to request the slave device to correct a transmission time point at which a first reference 1PPS signal is transmitted during a second period of the i.sup.th second. The compensation estimation circuit is coupled to the processing circuit and is configured for receiving the first reference 1PPS signal from the slave device during the second period of the i.sup.th second and determining second phase compensation information transmitted to the slave device according to a receiving time point at which the first reference 1PPS signal is received during a first period of an (i+1).sup.th second ) .
However, US 20230164725 does not explicitly teach transmit, by the first of the plurality of RIU, a message to a second of the plurality of RIUs.
US 20240255898, from the same or similar fields of endeavor, teaches synchronize a plurality of remote interface units ( Grand Master Clock 100, node 10A, node 40 ) [see Figure 7] to a single network time, the plurality of RIUs being connected in a network [see Paragraphs 0101 – 0106];
Receive, by a first (node 10A) of the plurality of RIUs, a one pulse per second (1pps) signal [see Paragraph 0096];
Transmit, by the first (node 10A ) of the plurality of RIUs , a message (PTP packet) to a second ( node 40 ) of the plurality of RIUs , the message (PTP) including the 1pps receive time and 1pps period, and the second (40) [see Figure 7] of the plurality of RIUs being one of the plurality of RIUs other than the first (10A) of the plurality of RIUs [see Paragraphs 0096 & 0101-0106].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the system of US 20230164725 in view of US 20240255898 because US 20240255898 suggests that an object of the present disclosure made in view of the above-described problems is to provide a measurement instrument, a measurement method, and a time synchronization system capable of relaxing the above-described constraints and measuring the accuracy of the in-device time more simply.
Regarding to the claim 18, claim 18 is rejected the same limitations of the claim 11 above.
Regarding to the claim 20, claim 20 is rejected the same limitations of the claim 13 above.
Regarding to the claim 1, US 20230164725 teaches a method comprising:
synchronize a plurality of remote interface units (master device , slave device ) [see Figures 3-4 ] to a network time, the plurality of RIUs ( master device, slave device ) being connected in a network [see Figures 3-4 and Paragraphs 0025-0026 ];
receiving, by a first ( slave device ) [see Figures 3-4 and Paragraphs 0025-0026 ] of the plurality of RIUs ( master device , slave device ) , a one pulse-per-second (1PPS) signal;
determine a 1PPS receive time (determining the receiving the synchronization signal frame from the master device during first period ) [see Figure 3] ( 413 , receive time) [see Figure 4 ] and a 1PPS period (T1 period ) [see Figure 4 ]based on the 1PPS signal and with respect to the single network time, the 1PPS receive time being when the 1PPS signal is received by the first (slave device ) of the plurality RIUs [see Figures 3-4 and Paragraphs 0025-0026 ]
( [0009] The disclosure further provides a master device including a processing circuit and a compensation estimation circuit. The processing circuit is configured to transmit a synchronization signal frame to a slave device during a first period of an i.sup.th second. The synchronization signal frame includes a synchronization header, a first pulse per second (1PPS) signal, first time of date information, and first phase compensation information. The first phase compensation information is configured to request the slave device to correct a transmission time point at which a first reference 1PPS signal is transmitted during a second period of the i.sup.th second. The compensation estimation circuit is coupled to the processing circuit and is configured for receiving the first reference 1PPS signal from the slave device during the second period of the i.sup.th second and determining second phase compensation information transmitted to the slave device according to a receiving time point at which the first reference 1PPS signal is received during a first period of an (i+1).sup.th second ) .
However, US 20230164725 does not explicitly teach transmit, by the first of the plurality of RIU, a message to a second of the plurality of RIUs.
US 20240255898, from the same or similar fields of endeavor, teaches synchronize a plurality of remote interface units ( Grand Master Clock 100, node 10A, node 40 ) [see Figure 7] to a single network time, the plurality of RIUs being connected in a network [see Paragraphs 0101 – 0106];
Receive, by a first (node 10A) of the plurality of RIUs, a one pulse per second (1pps) signal [see Paragraph 0096];
Transmit, by the first (node 10A ) of the plurality of RIUs , a message (PTP packet) to a second ( node 40 ) of the plurality of RIUs , the message (PTP) including the 1pps receive time and 1pps period, and the second (40) [see Figure 7] of the plurality of RIUs being one of the plurality of RIUs other than the first (10A) of the plurality of RIUs [see Paragraphs 0096 & 0101-0106].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the system of US 20230164725 in view of US 20240255898 because US 20240255898 suggests that an object of the present disclosure made in view of the above-described problems is to provide a measurement instrument, a measurement method, and a time synchronization system capable of relaxing the above-described constraints and measuring the accuracy of the in-device time more simply.
Regarding to the claim 4, claim 4 is rejected the same limitations of the claim 11 above.
Regarding to the claim 6, claim 6 is rejected the same limitations of the claim 13 above.
Claim(s) 10, 17, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. ( US 20230164725, hereinafter, Wang’s 725 ) in view of YAMAGATA ( US 20240255898, hereinafter, YAMAGATA’s 898, and further in view of SHIMIZU et al. ( US 20180062780, hereinafter, SHIMIZU’s 780 ).
Regarding to the claim 10, US 20230164725 and US 20240255898 teach the limitations of the claim 8 above.
However, US 20230164725 and US 20240255898 do not explicitly teach wherein the 1PPS signal originates from at least one of: a global positioning system (GPS);an Assured Positioning, Navigation, and Timing (A-PNT) device; a time sensitive network (TSN) Native Navigation Line Replaceable Unit (LRU);a radio beacon; a frequency standard; a precision oscillator; or an atomic clock.
US 20180062780, from the same or similar fields of endeavor, teaches wherein the 1PPS signal originates from at least one of: a global positioning system (GPS) ([0007] The IEEE 1588v2 PTP employs a hierarchical master-slave structure for clock distribution. The hierarchical master-slave structure comprises master nodes and slave nodes. The master node (a reference node that sends its local clock to external nodes) is also referred to as a grand master clock (GMC), and sends time information to the slave nodes according to the above-mentioned method (1). The master node itself corrects its local clock according to the above-mentioned method (2) in a case where the master node uses, as an external synchronization signal, a reference signal once every second (1PPS) generated by a global source clock (such as the GPS or an atomic clock).) [see Paragraph 0007 ] ;
an Assured Positioning, Navigation, and Timing (A-PNT) device;
a time sensitive network (TSN) Native Navigation Line Replaceable Unit (LRU);
a radio beacon;
a frequency standard;
a precision oscillator; or
an atomic clock (an atomic clock ) [see Paragraph 0007].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the combined system ( US 20230164725 and US 20240255898), and further in view of US 20180062780 because US 20180062780 suggests that the present invention has been made in view of the above problem, and an object thereof is to provide a time synchronization system including a plurality of master nodes which is capable of accurate and efficient time synchronization of the system entirely, for example, if one (secondary master node) of the plurality of master nodes has less clock accuracy. In the time synchronization system, the secondary master node synchronizes the time with the time in a primary master node and then synchronizes time with the time in an external synchronization signal.
Regarding to the claim 17, claim 17 is rejected the same limitations of the claim 10 above.
Regarding to the claim 3, claim 3 is rejected the same limitations of the claim 10 above.
Claim(s) 12, 19, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. ( US 20230164725, hereinafter, Wang’s 725 ) in view of YAMAGATA ( US 20240255898, hereinafter, YAMAGATA’s 898, and further in view of Wei et al. ( US 20240243829, hereinafter, Wei’s 829 ).
Regarding to the claim 12, US 20230164725 and US 20240255898 teach the limitations of the claim 8 above.
However, US 20230164725 and US 20240255898 do not explicitly teach wherein the message is a Time-Sensitive Network (TSN) message.
US 20240243829, from the same or similar fields of endeavor, teaches wherein the message is a Time-Sensitive Network (TSN) message ( wherein the message is a Time-Sensitive Network (TSN) message) [see Paragraphs 0120 – 0123 ].
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing data of the claimed invention to modify the combined system ( US 20230164725 and US 20240255898), and further in view of US 20240243829 because US 20240243829 suggests that the purpose of the present invention is to effectively conduct cross-network time synchronization to research time modeling and time error compensation models between synchronization nodes in the heterogeneous networks by taking the heterogeneous networks as objects in combination with statistical algorithms through synchronization modes such as IEEE 802.1AS, beacon frame synchronization and timestamp-free synchronization, so as to enhance cross-network time synchronization accuracy.
Regarding to the claim 19, claim 19 is rejected the same limitation of the claim 12 above.
Regarding to the claim 5, claim 5 is rejected the same limitation of the claim 12 above.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to disclose generating, by the second of the plurality of RIUs, a 1PPS clock based on at least the 1PPS receive time, the 1PPS period, and the single network time.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to disclose receiving, by a third of the plurality of RIUs, a second 1PPS signal, the third of the plurality of RIUs being one of the plurality of RIUs other than the first of the plurality of RIUs;determining a second 1PPS receive time and a second 1PPS period based on the second 1PPS signal and with respect to the single network time, the second 1PPS receive time being when the second 1PPS signal is received by the third of the plurality of RIUs; and transmitting, by the third of the plurality of RIUs and in response to the first of the plurality of RIUs being unable to transmit the message, a second message to a fourth of the plurality of RIUs in place of the message, the second message including the second 1PPS receive time and the second 1PPS period, and the fourth of the plurality of RIUs being one of the plurality of RIUs other than the third of the plurality of RIUs.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to disclose generate, by the second of the plurality of RIUs, a 1PPS clock based on at least the 1PPS receive time, the 1PPS period, and the single network time.
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to disclose receive, by a third of the plurality of RIUs, a second 1PPS signal, the third of the plurality of RIUs being one of the plurality of RIUs other than the first of the plurality of RIUs; determine a second 1PPS receive time and a second 1PPS period based on the second 1PPS signal and with respect to the single network time, the second 1PPS receive time being when the second 1PPS signal is received by the third of the plurality of RIUs; and transmit, by the third of the plurality of RIUs and in response to the first of the plurality of RIUs being unable to transmit the message, a second message to a fourth of the plurality of RIUs in place of the message, the second message including the second 1PPS receive time and the second 1PPS period, and the fourth of the plurality of RIUs being one of the plurality of RIUs other than the third of the plurality of RIUs.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to disclose generate, by the second of the plurality of RIUs, a 1PPS clock based on at least the 1PPS receive time, the 1PPS period, and the single network time.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUONG T HO whose telephone number is (571)272-3133. The examiner can normally be reached 7:30-4:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles C Jiang can be reached at 571-270-7191. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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CHUONG T. HO
Primary Examiner
Art Unit 2412
/CHUONG T HO/Examiner, Art Unit 2412
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