DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING CHANNEL PATTERN FORMED OF NANO-SHEETS AND EACH OF NANO-SHEETS INCLUDING AT LEAST ONE SUPERLATTICE LAYER
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 2022/0157811 A1; hereinafter “You”) in view of Yang et al. (US 2022/0271032 A1; hereinafter “Yang”).
Regarding claim 1, referring to at least Fig. 2A-2C and related text, You teaches a semiconductor device, comprising: a substrate (100) (paragraph 21); a first active pattern (AP1) on the substrate (paragraph 23); a first channel pattern (CH1) on the first active pattern, the first channel pattern comprising a first semiconductor pattern (SP2) and a second semiconductor pattern (SP3) on the first semiconductor pattern (paragraphs 25-26); a first source/drain pattern (SD1) connected to the first channel pattern (paragraph 27); and a gate electrode (GE1) on the first channel pattern (paragraph 32), wherein the first semiconductor pattern has a first length (SP2 having a length in D1 direction), wherein the second semiconductor pattern has a second length (SP3 having a length in D1 direction), and wherein the first length is greater than the second length (the length of SP2 is greater than the length of SP3) (Figs. 2C and 6B).
While You teaches that each of the first semiconductor pattern and the second semiconductor pattern comprises: a semiconductor layer (for example, each of SP2 and SP3 including silicon) (paragraph 26), You does not explicitly teach that the each of the first semiconductor pattern and the second semiconductor pattern comprises: a plurality of semiconductor layers; and at least one superlattice layer between adjacent semiconductor layers. Yang teaches a semiconductor device (a gate-all-around nanowire FET device) (Fig. 1 and paragraph 3), which is in the same technical field to that of You, comprising: a channel pattern (14P) comprising a first semiconductor pattern (a bottom one of 14P) and a second semiconductor pattern (a top one of 14P) (Fig. 1 and paragraphs 23-24), wherein each of the first semiconductor pattern and the second semiconductor pattern comprises: a plurality of semiconductor layers (14A); and at least one superlattice layer (14B) between adjacent semiconductor layers for improving electrical performance of the semiconductor device (Fig. 1 and paragraphs 25-26 and 38). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of You with that of Yang in order to improve electrical performance of the semiconductor device. It is noted that the combined teaching of You with that of Yang would result that the first length of the at least one superlattice layer included in the first semiconductor pattern is greater than the second length of the at least one superlattice layer included in the second semiconductor pattern as claimed.
Regarding claim 3, You in view of Yang does not explicitly teach that a thickness of the at least one superlattice layer included in the second semiconductor pattern is different from a thickness of the at least one superlattice layer included in the first semiconductor pattern. Nevertheless, it would have been obvious to one of ordinary skill in the art to adjust the thickness of the superlattice layer for the first semiconductor pattern and/or the thickness of the superlattice layer for the second semiconductor pattern as a routine skill in the art to obtain the desired thickness ranges, including the thickness ranges such that the superlattice layer for the first semiconductor pattern and the thickness of the superlattice layer for the second semiconductor pattern being different as claimed. It has held that discovering an optimum or workable ranges involves only routine skill in the art. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation. In re Aller, 105 USPQ 233.
Regarding claim 4, Yang teaches wherein a thickness of the at least one superlattice layer is less than a thickness of each of the plurality of semiconductor layers (Fig. 2 and paragraph 26).
Regarding claim 5, Yang teaches wherein each of the plurality of semiconductor layers includes silicon, and wherein the at least one superlattice layer comprises at least one of germanium (Ge), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), and indium phosphide (InP) (paragraph 36. For example, 14P formed of silicon germanium).
Regarding claim 7, You teaches wherein the gate electrode comprises an inner electrode (PO3) between the first semiconductor pattern and the second semiconductor pattern (Fig. 2A).
Regarding claim 8, You in view of Yang teaches wherein the first source/drain pattern comprises a pair of first source/drain patterns (a pair of SD1) (You, Fig. 5A), and wherein the at least one superlattice layer connects the pair of first source/drain patterns to each other (You, Fig. 2A, SD1 contacting CH1 and Yang, Fig. 1, 14P having 14B between 14A).
Regarding claim 9, You teaches wherein the first channel pattern further comprises a third semiconductor pattern (SP1) below the first semiconductor pattern (Fig. 2C).
Regarding claim 10, You teaches wherein the third semiconductor pattern is located at a lowermost tier in the first channel pattern (Fig. 2C).
Allowable Subject Matter
Claims 2 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 are allowable over cited prior arts.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding semiconductor devices in claims 11 and 16, particularly in combination with the limitation that a number of the superlattice layers in a first tier of the plurality of nano-sheets is greater than a number of the superlattice layers in a second tier of the plurality of nano-sheets, the first tier being above the second tier in claim 11 and a number of the at least one superlattice layer in each of the plurality of nano-sheets increases in a direction from a lowermost nano-sheet among the plurality of nano-sheets toward an uppermost nano-sheet among the plurality of nano-sheets in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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