Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 9 and 20.
b. Claims 1-26 are pending on the application.
Drawings
2. The drawings were received on 12/21/2023. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 06/17/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 01/31/2024. The information disclosed therein was considered.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “The present disclosure” and “In an example” in page 1, line 2 and 3; respectively, which are implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 4, 8-11 and 13-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al (Patent No.: US 6,180,454 B1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Chang et al in Figures 1-3 are directly discloses an integrated circuit (IC) (a flash memory device 10, Figure 1), comprising:
a flash memory bit structure (a core region 11 such as a string 22 contain a plurality of memory cell in the flash memory device 10, Fig. 1A-1C and 2A) on a semiconductor substrate (a substrate 16, Fig. 1C and a substrate 40, Fig. 3H), the flash memory bit structure (a core region 11 such as a string 22 contain a plurality of memory cell in the flash memory device 10) comprising a word line structure (a word line WL1…WL16, Fig. 2B) and a first oxide layer (a top oxide 46c, Fig. 3H) disposed between the semiconductor substrate (the substrate 40, Fig. 3H) and the word line structure (a word line WL1…WL16), the first oxide layer (the top oxide 46c) being free of nitridation (a nitride 46b, Fig. 3H); and
a transistor structure (a select transistor 14, 24, 26, Figs 1C-1B, 2A and 3H) on the semiconductor substrate (the substrate 16, 40, Figs. 1C and 3H), the transistor structure including a gate structure (a control gate 17b, Fig. 1C and 56, Fig. 3H) and a gate oxide layer (a gate oxide 42, Fig. 3H) including nitridation (a nitride 46b, Fig. 3H), the gate oxide layer (a gate oxide 46a and 46c, Fig. 3H) being over the semiconductor substrate (the substrate 40), the gate structure (the gate transistor 56, Fig.3H) being over the gate oxide layer (the gate transistor 56 disposed over the gate oxide 42, Fig. 3H)(see at least in Figures 1A-3H, column 1, lines 10-65 and column 9, lines 39 to column 12, lines 7 and the related disclosures).
Regarding dependent claim 4, Chang et al in Figures 1-3 are directly discloses an integrated circuit (IC) (a flash memory device 10, Figure 1), wherein the word line (the word line WL1…WL16) structure includes polysilicon (Poly 1, Fig. 2B, column 2, lines 6-7).
Regarding dependent claim 8, Chang et al in Figures 1-3 are directly discloses an integrated circuit (IC) (a flash memory device 10, Figure 1), wherein the transistor structure includes a p-channel transistor (the P-well substrate 16 includes a channel 15, Fig. 1C) with a SiGe structure (the memory cell 14 typically includes the source 14b, the drain 14a and a channel 15 in a substrate or P-well 16, Fig. 1C).
Regarding claims 9-11 and 13-14, they encompass the same scope of invention as that of claims 1, 4 and 8, except they draft the invention in method format instead of apparatus format. Chang et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claims 9-11 and 13-14, are therefore rejected in method format for the same reasons claims 1, 4 and 8, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
6. Claims 2-3, 5-7, 12 and 15-19, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 2, the prior art fails to tech or suggest the claimed limitations, namely, the flash memory bit structure further comprises: a floating gate structure, the word line structure being located at a first side of the floating gate structure; an erase gate structure located at a second side of the floating gate structure opposite the first side; and a second oxide layer disposed between the erase gate structure and the floating gate structure, the second oxide layer being free of nitridation.
With respected to dependent claim 3, the prior art fails to tech or suggest the claimed limitations, namely, the flash memory bit structure further comprises: a floating gate structure; a control gate structure over the floating gate structure; a second oxide layer disposed between the floating gate structure and the word line structure, the second oxide layer being free of nitridation; and a nitride layer over the floating gate structure and disposed between the second oxide layer and the control gate structure.
With respected to dependent claim 5, the prior art fails to tech or suggest the claimed limitations, namely, a transition region between the flash memory bit structure and the transistor structure, the transition region including: an isolation structure in the semiconductor substrate; and an oxide protrusion over the isolation structure extending vertically from an upper surface of the isolation structure.
With respected to dependent claim 6, the prior art fails to tech or suggest the claimed limitations, namely, a transition region between the flash memory bit structure and the transistor structure, the transition region including an isolation structure in the semiconductor substrate, the isolation structure having a recess from an upper surface of the isolation structure.
With respected to dependent claim 7, the prior art fails to tech or suggest the claimed limitations, namely, a transition region between the flash memory bit structure and the transistor structure, the transition region including: a first isolation structure in the semiconductor substrate, the first isolation structure proximate the transistor structure; a second isolation structure in the semiconductor substrate, the second isolation structure proximate the flash memory bit structure; and a portion of the semiconductor substrate extending between the first isolation structure and the second isolation structure, the portion of the semiconductor substrate surrounding the flash memory bit structure.
With respected to dependent claim 12, the prior art fails to tech or suggest the claimed limitations, namely, the nitriding is blocked from reaching the first oxide layer, at least in part, by the word line structure formed on the first oxide layer.
With respected to dependent claim 15, the prior art fails to tech or suggest the claimed limitations, namely, forming the flash memory bit structure further includes: forming a control gate structure over the floating gate structure; forming a nitride layer along a sidewall of the control gate structure; and forming a second oxide layer along a sidewall of the nitride layer, the second oxide layer being disposed between the word line structure and the nitride layer, wherein after nitriding the gate oxide layer, the second oxide layer is free of nitridation.
With respected to dependent claims 16-17, the prior art fails to tech or suggest the claimed limitations, namely, forming the flash memory bit structure further includes: forming a second oxide layer at a second side of the floating gate structure opposite the first side of the floating gate structure, the second oxide layer being on a sidewall of the floating gate structure; and forming an erase gate structure on the second oxide layer.
With respected to dependent claim 18, the prior art fails to tech or suggest the claimed limitations, namely, forming an isolation structure in the semiconductor substrate in a transition region between the flash memory bit structure and the transistor structure, wherein forming the word line structure includes patterning the word line structure, the isolation structure being exposed by patterning the word line structure; forming a protective oxide on a sidewall of the word line structure and extending over the isolation structure that was exposed by patterning the word line structure; forming a gate structure over the gate oxide layer; and after forming the gate structure, etching the protective oxide, wherein a photoresist used in the etching has an opening defined in part by a photoresist sidewall, a gap being laterally between the photoresist sidewall and the protective oxide laterally distal form the word line structure, the opening exposing the protective oxide and a portion of the isolation structure, the etching forming a recess in the isolation structure.
With respected to dependent claim 19, the prior art fails to tech or suggest the claimed limitations, namely, forming an isolation structure in the semiconductor substrate in a transition region between the flash memory bit structure and the transistor structure, wherein forming the word line structure includes patterning the word line structure, the isolation structure being exposed by patterning the word line structure; forming a protective oxide on a sidewall of the word line structure and extending over the isolation structure that was exposed by patterning the word line structure; forming a gate structure over the gate oxide layer; and after forming the gate structure, etching the protective oxide, wherein a photoresist used in the etching has an opening defined in part by a photoresist sidewall, the photoresist sidewall being over the protective oxide, the etching forming a protrusion oxide protruding from the isolation structure, the protrusion oxide remaining from the protective oxide after the etch.
7. Claims 20-26 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 20: there is no teaching, suggestion, or motivation for combination in the prior art to the steps of “forming an oxide-nitride-oxide stack over the floating gate structure; forming a control gate structure over the oxide-nitride-oxide stack; forming a word line oxide layer over the semiconductor substrate laterally on a first side of the floating gate structure; forming a word line structure over the word line oxide layer; after forming the word line structure, forming a gate oxide layer; and forming a gate electrode over the gate oxide layer” in a method as claimed in the independent claim 20. Claims 21-26 are also allowed because of their dependency on claim 20.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Min et al (US. 7,230,305 B2) discloses a flash memory cell array region and a mask rom cell array region.
Shukuri et al (US. 6,528,839 B2) discloses a flash memory, a logic circuit and external input/output circuit in semiconductor.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights