Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 12/21/2023.
Drawing
The drawings filed on 12/21/2023 are acceptable.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 04/29/2025 and 10/07/2025 are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDSs have been considered by the examiner.
Claims 1-8 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 10,551,224 B2A1), hereinafter ‘Kobayashi.
In re to claim 1, Kobayashi disclose an integrated controller for a buck converter (i.e. the power converter controller, see figs. 7 and 8) comprising: a controller (i.e. 2) coupled to receive a feedback signal indicative of an output voltage (i.e. signal indicative of VC) of the buck converter and responsive to the feedback signal to produce an input drive signal (i.e. control circuit 2 generating first drive signal S2 as controlled by the voltage detector 6, see fig. 8 and col. 14, lines 28-35); a bias drive circuit (i.e. SW,CS and MN1, fig. 8) coupled to the controller (i.e. 2) and responsive to the input drive signal (i.e. at the input of SW) to produce a bias drive signal (when SW is closed, VDD, CS and MN1 generate a bias drive signal that is equal to the gate voltage of MN1); a bias supply circuit (i.e. 5) comprising, a bias transistor (i.e. MN2) having a gate coupled to receive the bias drive signal (i.e. CS), and a bias diode (i.e. D3), an anode of the bias diode coupled to a drain of the bias transistor (i.e. the drain of MN2) and a cathode of the bias diode coupled to the bias drive circuit (i.e. the cathode of D3 connected to SW of the bias drive circuit), wherein the bias transistor responsive to the bias drive signal being asserted conducts such that there is a voltage drop across the bias transistor(i.e. when SW is closed and a voltage is generated on the gate MN1, MN2 is turned on); and an output conduction detector circuit (i.e. 6) coupled to a source and to a drain of the bias transistor (i.e. MN2), the output conduction detector circuit responsive to detecting the voltage drop to produce an output conduction signal (i.e. see col.13, line 66 to col. 14, line 53). With respect to claim 4, Kobayashi et al. discloses that it preferable to construct the second drive circuit (6) and the bias driver circuit (5) on the same monolithic integrated circuit/single integrated circuit package (i.e., on the “same chip”). Kobayashi et al. further discloses that “other circuits” may be integrated on the “same chip” to allow for a construction of the circuit that has a low cost and a reduced size (see Col. 13 lines 54-62). Except, Kobayashi fail to explicitly disclose that integrated controller circuit. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate as many of the devices as possible (I.e. including 6, 2 and 5, fig. 8) within the same chip, since it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
In re to claim 2, Kobayashi disclose the integrated controller (i.e. the power converter controller, see figs. 7 and 8) as in claim 1, the output conduction detector circuit (i.e. 6, fig. 6) comprising a comparator (i.e. 8) coupled to compare a voltage at the drain of the bias transistor (i.e. voltage of drain of MN2, fig. 6) and a threshold voltage (i.e. VDD) to produce the output conduction detector signal (i.e. DET, see fig. 6 and col. 12. Lines 16-48). Except, Kobayashi fail to explicitly disclose that integrated controller circuit. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate as many of the devices as possible (including 6, 2 and 5) within the same chip, since it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
In re to claim 3, Kobayashi disclose the controller (i.e. the power converter controller, see figs. 7 and 8) as in claim 2, wherein the input drive circuit and the output drive circuit are included in a single integrated circuit package. Kobayashi disclose that it is preferable to construct the second drive circuit (i.e. 6) and the bias driver circuit (i.e. 5) in a single integrated circuit package. Kobayashi further disclose that “other circuits” may be integrated on the “same chip” to allow for a construction of the circuit that has a low cost and a reduced size (see Col. 13 lines 54-62). However, Kobayashi fails to disclose explicitly that wherein the input drive circuit and the output drive circuit are included in a single integrated circuit package. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate as many of the devices as possible (including 6, 2 and 5) within a single integrated circuit package, since it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
In re to claim 4, Kobayashi disclose the controller (i.e. the power converter controller, see figs. 7 and 8) as in claim 2, wherein the input drive circuit and the output drive circuit are included in a monolithic integrated circuit. Kobayashi disclose that it is preferable to construct the second drive circuit (i.e. 6) and the bias driver circuit (i.e. 5) in a monolithic integrated circuit. Kobayashi further disclose that “other circuits” may be integrated on the “same chip” to allow for a construction of the circuit that has a low cost and a reduced size (see col. 13 lines 54-62). However, Kobayashi fails to disclose explicitly that wherein the input drive circuit and the output drive circuit are included in a monolithic integrated circuit. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate as many of the devices as possible (including 6, 2 and 5) within a monolithic integrated circuit, since it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
Allowable Subject Matter
Claims 5-8 are allowed over the art of record.
The following is an examiner’s statement of reasons for allowance: -
In re to claim 5, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “a bias capacitor coupled to the output filter circuit; an output conductor circuit coupled to the output filter circuit; a controller coupled to the output filter circuit, the controller comprising, an output drive circuit coupled to the output filter circuit, the output drive circuit configured to receive the feedback signal; an input drive circuit coupled the output drive circuit, the input drive circuit responsive to the feedback signal to produce an input drive signal; a bias drive circuit coupled to the bias capacitor and to the input drive circuit, the bias drive circuit responsive to the input drive signal to produce a bias drive signal”.
The art of record does not disclose the above limitations, nor would it be obvious to modify the art of record to include either of the above limitations.
In re to claims 6-8, claims 6-8 depend on claim 5, thus are also allowed for the same reasons provided above.
Remarks
The Office has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838