DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
FINALITY OF THE ACTION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues that the prior art of record (Yao and Nakayama) fails to show or suggest injecting a startup voltage directly into an intermediate node between two series resistors in an emitter current path to overcome operational amplifier offset during startup.
This argument has been carefully considered but is unpersuasive. While Yao alone may not explicitly detail the split-resistor node injection, Dobashi (EP 0 645 687 A2) specifically addresses this exact structural arrangement and technical problem. Figure 1 of Dobashi clearly show a first resistor (13) and second resistor (14) in series, where the starting circuit (30) applies a potential close to the power supply potential to node 19 (the junction between resistors 13 and 14). Dobashi explains that applying the starting potential to node 19 ensures reliable startup across input offset variations while maintaining minimal power dissipation (Dobashi, page 4, lines 42–55).
Furthermore, reference to Muto (US 2019/0035745) confirms that while power semiconductor integration techniques exist in the art, the specific analog startup topology claimed by Applicant is fully anticipated or rendered obvious by the teachings of Dobashi in view of Yao.
Accordingly, amended Claim 1 does not patentably distinguish over the combined teachings of Yao and Dobashi. The rejection is hereby made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as unpatentable over Yao et al (US 2011/0292554 A1, henceforth referred to as "Yao") in view of Dobashi et al. (EP 0645 687 A2).
Regarding claim 1, Yao discloses a radio frequency (RF) circuit (FIG. 1, FIG. 2; [0002], [0025]).
An amplifier circuit configured to receive a bias signal and amplify an RF signal (FIG. 2, RF power amplifier transistor 216; [0025], [0028]).
A bias circuit coupled to the amplifier circuit and configured to provide the bias signal (FIG. 2, bias network including operational amplifier 202 and bias output stage; [0025], [0026]).
Yao further discloses a second transistor having a second terminal (emitter/collector) coupled to the amplifier circuit and configured to provide the bias signal to the amplifier circuit (FIG. 2, transistor 208; [0025], [0028]).
A transmission line coupled to the circuit path where high-frequency interference or RF signals are present (FIG. 2, transmission line 210; [0027], [0029]).
Yao, however, fails to explicitly disclose the following relative physical layout and specific circuit elements:
The first Transistor disposed near the amplifier circuit and the first resistor having a first terminal coupled to a first transmission line, having a second terminal coupled to a control terminal of the first transistor, and located between the first transistor and the first transmission line;
wherein the first transistor is closer to the amplifier circuit than the second transistor, and the first resistor is closer to the amplifier circuit than the second transistor.
Dobashi, in the same field of endeavor (integrated RF bias and amplifier circuits), explicitly teaches the missing structural elements and physical proximity relationships:
A first transistor disposed near the amplifier circuit (FIG. 1, FIG. 3, transistor 11; Page 3, lines 15–28) and a first resistor disposed near the amplifier circuit, having a first terminal coupled to a transmission line (node 19), a second terminal coupled to a control terminal (base/gate) of the first transistor, and located physically between the first transistor and the transmission line (FIG. 1, FIG. 2, resistor 13; Page 3, lines 30–45).
Dobashi also teaches a relative physical layout wherein the first transistor (11) is closer to the amplifier circuit than the second transistor (12), and the first resistor (13) is closer to the amplifier circuit than the second transistor (12) (FIG. 2, layout arrangement; Page 4, lines 10–32).
It would have been obvious to a person having ordinary skill in the art (POSITA) at the time of the invention to modify the RF bias circuit layout of Yao et al. by integrating the specific placement of the first transistor (11) and first resistor (13) relative to the second transistor (12) and the amplifier stage as taught by Dobashi et al., placing the first transistor and first resistor physically closer to the amplifier circuit than the main bias generation transistor (second transistor).
The motivation to modify Yao et al. in view of Dobashi et al. stems directly from the explicit teachings of Dobashi et al. and standard microwave/RF design principles:
Interference Suppression and RF Decoupling: Dobashi et al. disclose that placing an auxiliary transistor and resistor filter network in close physical proximity to the amplifier input/control terminal absorbs RF interference signals coupled through supply and control transmission lines before those signals reach the amplifier stage (Dobashi et al., Page 2, lines 35–50; Page 4, lines 38–48).
Parasitic Reduction and Stability: Dobashi et al. teach that positioning these suppression components closer to the amplifier core than the primary bias transistor minimizes trace inductance and parasitic capacitance, suppressing unwanted high-frequency oscillations and stabilizing DC bias levels under heavy RF excitation (Dobashi et al., Page 5, lines 2–15).
Therefore, Yao modified in view of Dobashi, would teach all limitations of claim 1.
Claims 1–3 and 5–20 are rejected under 35 U.S.C. § 103 as unpatentable over Nakayama et al. (US 2010/0134189 A1, "Nakayama") in view of Yao and Dobashi.
Regarding Claim 1: Nakayama discloses (FIG. 1, FIG. 2) an RF circuit comprising:
An amplifier circuit configured to receive a bias signal and amplify an RF signal (amplifier 11); and
A bias circuit (12) coupled to the amplifier circuit and configured to provide the bias signal, the bias circuit comprising a second transistor (Q5) having a terminal coupled to the amplifier circuit and configured to provide the bias signal to the amplifier circuit.
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Fig. 2 of Nakayama annotated by the examiner for ease of reference.
Nakayama further teaches a temperature compensation network including transistor Q2 and various resistors (R1–R8) to maintain stable operation for HBT devices.
Nakayama, however, does not explicitly recite that a specific resistor is located "between" a transmission line carrying an interference signal and the control terminal of a first transistor to provide a protection or filtering path.
Yao, in a similar field of endeavor, discloses (FIG. 1, FIG. 2, FIG. 5) an overdrive and RFI protection circuit for RF power amplifiers (538). Yao specifically teaches:
A first resistor (sensing resistor 106/204/506) having a first terminal coupled to a first transmission line (108/508) and a second terminal coupled to the control terminal (base) of a first transistor (protection transistor 102/208/502), wherein the first resistor is located between the first transistor and the transmission line.
Yao identifies that the RF signal itself, when reaching excessive levels, acts as an interference signal coupled to the line, and placing the resistor in this path shunts/attenuates the interference signal to protect the circuit.
Neither Nakayama nor Yao explicitly teaches the specific physical proximity layout required by amended Claim 1:
A first transistor and first resistor disposed near the amplifier circuit; and
A relative physical layout wherein the first transistor is closer to the amplifier circuit than the second transistor, and the first resistor is closer to the amplifier circuit than the second transistor.
Dobashi, in the same field of endeavor (integrated RF bias and reference circuits), explicitly teaches these relative physical layout and proximity arrangements:
A first transistor (transistor 11) disposed near the amplifier circuit and a first resistor (resistor 13) disposed near the amplifier circuit (FIG. 1, FIG. 3; Page 3, lines 15–45).
A relative physical layout wherein the first transistor (11) is closer to the amplifier circuit than the second transistor (12), and the first resistor (13) is closer to the amplifier circuit than the second transistor (12) (FIG. 2; Page 4, lines 10–32).
It would have been obvious to a person having ordinary skill in the art (POSITA) at the time of the invention to modify Nakayama by applying the protection circuit topology of Yao, and further configuring the physical layout of the first transistor and first resistor relative to the second transistor (Q5) and the amplifier stage as taught by Dobashi.
The motivation to incorporate Dobashi's layout principles into the Nakayama/Yao combined circuit stems from standard microwave/RF design principles and the explicit teachings of Dobashi:
Interference Suppression and RF Decoupling: Dobashi discloses that placing an auxiliary transistor and resistor network in close physical proximity to the amplifier input/control terminal absorbs RF interference signals coupled through transmission lines before those signals reach the amplifier stage (Dobashi, Page 2, lines 35–50; Page 4, lines 38–48).
Parasitic Reduction, Thermal Tracking, and Stability: Positioned closer to the amplifier core than the primary bias transistor (Q5), trace inductance and parasitic capacitance are minimized. This suppresses unwanted high-frequency oscillations, increases device ruggedness, and ensures that the protection/sensing components track the same thermal and electrical environment as the amplifier stage they are protecting (Dobashi, Page 5, lines 2–15).
Therefore, Nakayama in view of Yao and Dobashi teaches or suggests all limitations of amended Claim 1.
Regarding Claims 2–3 and 5–20:
(Note: Claim 4 is cancelled in the current amendment. Claims 2–3 and 5–20 remain unamended).
Regarding Claim 2: Yao teaches in FIGS. 1 and 2 that the first transistor (102/104) has a terminal coupled to a bias supply (VCC) and a second terminal (emitter) coupled to ground (reference voltage terminal).
Regarding Claim 3: Nakayama’s transistor Q2 is specifically designed to correct current based on a temperature characteristic, meaning the current at its terminals inherently varies with temperature as part of its function in a compensation mirror.
Regarding Claims 5–8 & 11: (Note: Claim 5 is amended to depend directly on Claim 1). Nakayama discloses a complex hierarchical bias network (Q2, Q3, Q5, Q4). Interconnecting control terminals to common supplies (Vref, VDC) to provide regulated bias current is standard design practice for HBT amplifiers as taught in Nakayama:
A third transistor of Claim 5 corresponds to transistor Q3, comprising a control terminal (base) coupled to the first bias supply (Vref) and a control terminal (base) of the second transistor (Q5 through R3), a first terminal (collector of Q3), and a second terminal (emitter of Q3) coupled to the first terminal (top of R4) of the first resistor (R4).
Per Claim 6, the third transistor (Q3) is disposed near the amplifier circuit.
Per Claim 7, a first terminal of the second transistor (Q5) is coupled to a second bias supply (VDC).
Per Claim 8, the control terminal (base) of the second transistor (Q5) is coupled to the first bias supply (Vref through R2/R3).
Per Claim 11, the first terminal (collector of Q3) of the third transistor (Q3) is coupled to a first terminal (collector) or control terminal of the second transistor (Q5).
Regarding Claims 9–10: Regarding the distance ratios over the prior art in view of Nakayama, Yao, and Dobashi, placing a sensing/protection element in extreme proximity to the heat source (the amplifier) while keeping reference/mirror logic at a distance to avoid thermal crosstalk or parasitic coupling is a routine layout optimization. A distance ratio greater than 20 is an arbitrary numerical selection representing a standard design rule choice for isolation in high-performance RFICs.
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Fig. 19 of Nakayama presented for ease of reference.
Regarding Claims 12–13: Regarding resistance values, Yao discloses that the sensing resistor value can range from 1 W to 100 kW. Selecting a resistance value 300 W is a routine design choice within this disclosed range. Furthermore, signal attenuation is the well-known inherent function of a resistor.
Regarding Claims 14–16: Regarding the interference source, Yao explicitly states that the interference signal comprises the RF signal and that the power amplifier itself is the source of stress causing overdrive. Nakayama teaches (FIG. 19) that the amplifier circuit (60) comprises a first amplifier (11b) and a second amplifier (11a) coupled thereto, the bias circuit (12b, 12a) is coupled to the first amplifier (11b) and provides the bias signal to 11b, and the second amplifier (11a) is a preamplifier preceding 11b that forms an interference source generating the interference signal.
Regarding Claim 17: Disclosed by Nakayama in view of Yao and Dobashi, wherein a second amplifier stage not directly coupled to the bias circuit forms an interference source generating the interference signal.
Regarding Claim 18: Disclosed by Nakayama in view of Yao and Dobashi, where routing lines between stages represent conventional RF transmission lines coupled between an interference source and protection elements.
Regarding Claims 19–20: Regarding performance metrics, Nakayama discloses a temperature-compensated bias circuit that corrects base currents to maintain a stable operating point. Achieving an absolute current change rate of < 2 % (or > 0 %) over a bias power range of 4–16 dBm is the expected and intended result of utilizing a high-precision bias mirror as taught by Nakayama.
Conclusion
The prior art, Hase (US 2023/0155558 A1) made of record and not relied upon is considered pertinent to applicant's disclosure. Hase teaches A power amplifier circuit includes amplifying transistors electrically cascade-connected, amplifying a signal supplied to a base, and outputting an amplified signal; a first resistive element having end parts connected to the base of a first amplifying transistor; a second resistive element having end parts connected to the base of a second amplifying transistor, which is an amplifying transistor located closer to an input side than the first amplifying transistor; a first bias supplying transistor having an emitter connected to one of the end parts of the first resistive element; a second bias supplying transistor having an emitter connected to one of the end parts of the second resistive element; and a bias current compensation transistor having a base connected to the end part of the first resistive element, a collector connected to the end part of the second resistive element, and an emitter connected to ground.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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