DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The information disclosure statements filed 12/22/2023 and 3/19/2024 have been entered. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-10 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Chiu et al. (Chiu et al. – 2021/0005979; herein after referred as to “Chiu”).
Regarding claim 1, Chiu discloses a liquid crystal phase shifter, comprising:
a first transistor, with a first end electrically connected to a source line, with a control end configured to receive a first control signal (Chiu; Fig. 1A-1C; 2A-2D; 3, thin film transistor 600, 606a connected to data line DL, 606b connected to scan line SL);
a storage capacitor, with a first end electrically connected to a second end of the first transistor, with a second end electrically connected to an auxiliary source line (Chiu; Fig. 1A-1C, 2A-2D,3 , 4, 9, 18A-18D; par. 0128-0131, 0169-0172; thin film transistor 600, 606a connected to data line DL, 606b connected to scan line SL, Cst – storage capacitor to maintain a voltage to compensate the phase shifter);
a phase shifting electrode, electrically connected to the second end of the first transistor (Chiu; Fig. 1A-1C, 2A-2D, 3, 4, 9, 18A-18D; par. 0042-0046, 0128-0131, 0169-0172; patch element 204, thin film transistor 600, 606a connected to data line DL, 602 connected to scan line SL, source electrode 606b is conned to feeding structure 400 which is connected to a feeding source FS, FS is source voltage with reference to ground, Cst – storage capacitor to maintain a voltage to compensate the phase shifter, phase shifter electrodes 500 – microstrip; storage capacitor Cst connected to phase shifter electrodes, the phase shifting circuits and path elements are arranged in rows of a matrix in the manner as shown in Fig. 4)6; and
a common electrode, configured to receive a ground voltage, wherein the common electrode and the phase shifting electrode form a liquid crystal capacitor, wherein the liquid crystal phase shifter is attached to a feeding plate, and wherein the common electrode of the liquid crystal phase shifter and a microstrip feed line of the feeding plate form a microstrip antenna (Chiu; Fig. 1A-1C, 2A-2D, 3, 4, 9, 18A-18D; par. 0042-0046, 0128-0131, 0169-0172; patch element 204, thin film transistor 600, 606a connected to data line DL, 602 connected to scan line SL, source electrode 606b is conned to feeding structure 400 which is connected to a feeding source FS, FS is source voltage with reference to ground, Cst – storage capacitor to maintain a voltage to compensate the phase shifter, phase shifter electrodes 500 – microstrip; storage capacitor Cst connected to phase shifter electrodes, the phase shifting circuits and path elements are arranged in rows of a matrix in the manner as shown in Fig. 4).
Regarding claim 8, Chui discloses a liquid crystal phase shifter, comprising:
a phased array, comprising:
a plurality of first phase shifting circuits, arranged in a plurality of rows of a matrix, wherein the first phase shifting circuits comprise a plurality of first transistors, a plurality of first storage capacitors and a plurality of phase shifting electrodes electrically connected to first ends of the first storage capacitors (Chiu; Fig. 1A-1C, 2A-2D, 3, 4, 9, 18A-18D; par. 0042-0046, 0128-0131, 0169-0172; patch element 204, thin film transistor 600, 606a connected to data line DL, 602 connected to scan line SL, source electrode 606b is conned to feeding structure 400 which is connected to a feeding source FS, FS is source voltage with reference to ground, Cst – storage capacitor to maintain a voltage to compensate the phase shifter, phase shifter electrodes 500 – microstrip; storage capacitor Cst connected to phase shifter electrodes, the phase shifting circuits and path elements are arranged in rows of a matrix in the manner as shown in Fig. 4); and
a first source line, electrically connected to first ends of the first transistors, wherein second ends of the first transistors are electrically connected to the first ends of the first storage capacitors, respectively; a first auxiliary source line, electrically connected to second ends of the first storage capacitors; and a common electrode, wherein the common electrode and the first phase shifting electrodes form a plurality of first liquid crystal capacitors, and wherein the common electrode is configured to receive a ground voltage (Chiu; Fig. 1A-1C, 2A-2D, 3, 4, 9, 18A-18D; par. 0042-0046, 0128-0131, 0169-0172; patch element 204, thin film transistor 600, 606a connected to data line DL, 602 connected to scan line SL, source electrode 606b is conned to feeding structure 400 which is connected to a feeding source FS, FS is source voltage with reference to ground, Cst – storage capacitor to maintain a voltage to compensate the phase shifter, phase shifter electrodes 500 – microstrip; storage capacitor Cst connected to phase shifter electrodes, the phase shifting circuits and path elements are arranged in rows of a matrix in the manner as shown in Fig. 4).
Regarding claim 9, Chiu discloses the liquid crystal phase shifter of claim 8, wherein the common electrode of the liquid crystal phase shifter and a microstrip feed line of a feeding plate form a microstrip antenna (Chiu; Fig. 1A-1C, 2A-2D, 3, 4, 9, 18A-18D; par. 0042-0046, 0128-0131, 0169-0172; patch element 204, thin film transistor 600, 606a connected to data line DL, 602 connected to scan line SL, source electrode 606b is conned to feeding structure 400 which is connected to a feeding source FS, FS is source voltage with reference to ground, Cst – storage capacitor to maintain a voltage to compensate the phase shifter, phase shifter electrodes 500 – microstrip; storage capacitor Cst connected to phase shifter electrodes, the phase shifting circuits and path elements are arranged in rows of a matrix in the manner as shown in Fig. 4).
Regarding claim 10, Chui discloses the liquid crystal phase shifter of claim 8, further comprising: a source driving circuit, electrically connected to the first phase shifting circuits, and wherein an output range of the source driving circuit does not include negative voltage range (Chiu; Fig. 1A-1C, 2A-2D, 3, 4, 9, 18A-18D; par. 0042-0046, 0128-0131, 0169-0172; patch element 204, thin film transistor 600, 606a connected to data line DL, 602 connected to scan line SL, source electrode 606b is conned to feeding structure 400 which is connected to a feeding source FS, FS is source voltage with reference to ground, Cst – storage capacitor to maintain a voltage to compensate the phase shifter, phase shifter electrodes 500 – microstrip; storage capacitor Cst connected to phase shifter electrodes, the phase shifting circuits and path elements are arranged in rows of a matrix in the manner as shown in Fig. 4).
Allowable Subject Matter
Claims 12-20 are allowed.
Claims 2-7, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to disclose:
i. The liquid crystal phase shifter of claim 1, further comprising: a second transistor, with a first end configured to receive the ground voltage, with a second end electrically connected to the auxiliary source line, with a control end configured to receive a second control signal; a source driving circuit; and a third transistor, with a first end electrically connected to the auxiliary source line, with a second end electrically connected to the source driving circuit, with a control end configured to receive a third control signal (the prior art fails to disclose the second transistor and the connections set forth in claim 2; claims 3-7 depend on claim 2).
ii. The liquid crystal phase shifter of claim 8, wherein control ends of the first transistors are configured to receive a plurality of first control signals, respectively, and wherein the phased array further comprises: a plurality of second phase shifting circuits, arranged in the rows of the matrix, wherein the second phase shifting circuits comprise a plurality of fourth transistors, a plurality of second storage capacitors and a plurality of second phase shifting electrodes electrically connected to first ends of the second storage capacitors, wherein the common electrode and the second phase shifting electrodes form a plurality of second liquid crystal capacitors, and wherein control ends of the fourth transistors are configured to receive the first control signals, respectively; a second source line, electrically connected to first ends of the fourth transistors; and a second auxiliary source line, electrically connected to second ends of the second storage capacitors, and wherein the source driving circuit is electrically connected to the second source line and the second auxiliary source line (the prior fails to disclose the fourth transistor, the second storage capacitors and interconnections as recited claim 11).
iii. An antenna device as recited in claim 12, comprising:
a feeding plate, comprising:
a circuit board;
a microstrip feed line; and
a ground layer, wherein the ground layer and the microstrip feed line are disposed in opposite surfaces of the circuit board; and
a liquid crystal phase shifter, attached to the feeding plate, wherein the liquid crystal phase shifter overlaps a portion of the microstrip feed line, and wherein the liquid crystal phase shifter comprises:
a first substrate;
a phased array, formed on the first substrate;
a liquid crystal layer;
a second substrate; and
a common electrode, formed on the second substrate, wherein the liquid crystal layer is disposed between the phased array and the common electrode, wherein the common electrode is electrically connected to the ground layer, and wherein the common electrode of the liquid crystal phase shifter and the microstrip feed line of the feeding plate form a microstrip antenna (the prior art fails to disclose the layers as recited in claim 12; claims 13-20 depend on claim 12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN MINH LE whose telephone number is (571)272-2396. The examiner can normally be reached 6:30-5:00 PM M-Th..
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/THIEN M LE/Primary Examiner, Art Unit 2876