Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/15/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Korner (US 2019/0386652) in view of Vielemeyer et al. (97999643).
Regarding claim 1, Korner discloses a semiconductor switch [figs. 1-3A] comprising a first main terminal [connection of 230 and 238, figs. 1 and 3A], a second main terminal [connection of 232 and 240, figs. 1 and 3A], and a control terminal [211, par. 0032-0034]; a high voltage HEMT [226, par. 0036], and at least part of an interface circuit [212], the high voltage HEMT including a high voltage HEMT source terminal [232], a high voltage HEMT drain terminal [230], and a high voltage HEMT gate terminal [228]; a high voltage transistor device [234, par. 0035-0037], the high voltage transistor device comprising a transistor device [238] first terminal [234], a transistor device second terminal [240], and a transistor device gate terminal [236]; wherein the high voltage HEMT source terminal [232] and the transistor device first terminal are operatively connected to the first main terminal; wherein the high voltage HEMT drain terminal [230] and the transistor device second terminal are operatively connected to the second main terminal; and wherein the high voltage HEMT gate terminal [228] is operatively connected to the control terminal via the interface circuit [212], wherein the interface circuit is configurable to adjust a voltage applied to the control terminal to be operatively compatible with the high voltage HEMT gate terminal [par. 0039-0040]; and wherein the transistor device gate terminal [228] is operatively connected to the control terminal [211, through 212, see figs. 1-3A]. Korner does not explicitly disclose a III-nitride integrated circuit, comprising: a high voltage HEMT and at least part of an interface circuit.
However, Vielemeyer discloses (abstract and fig. 5) a III-nitride integrated circuit [100], comprising: a high voltage HEMT [102] and at least part of an interface circuit [202/204]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner as taught in Vielemeyer in order to provide at least part of a gate driver (an interface circuit) is monolithically integrated with a power HEMT on the same die. Such an integrated structure eliminates much of the parasitic inductance seen by the gate of the power HEMT, reducing voltage spikes at the gate of the power HEMT [cl. 2, ln. 65 and cl. 3, ln. 1-17].
Regarding claim 4, Korner in view of Vielemeyer [figs. 1-2] wherein the transistor device gate terminal [238] is connected to the control terminal via the interface circuit.
Regarding claim 6, Korner in view of Vielemeyer discloses [figs. 1-2] wherein the high voltage transistor device is a silicon and/or silicon carbide transistor [par. 0035].
Regarding claim 7, Korner in view of Vielemeyer discloses [figs. 1-2] wherein the high voltage transistor device [234] comprises an insulated-gate bipolar transistor IGBT) [par. 0035], and wherein the transistor device first terminal is an IGBT emitter terminal and the transistor device second terminal is an IGBT collector terminal.
Regarding claim 8, Korner in view of Vielemeyer discloses [figs. 1-2] wherein the high voltage transistor device [234] comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) [par. 0035], and wherein the transistor device first terminal is a MOSFET source terminal [240] and the transistor device second terminal is a MOSFET drain terminal [238].
Regarding claim 10, Korner in view of Vielemeyer discloses [figs. 1-2] wherein the high voltage HEMT source terminal, the high voltage HEMT drain terminal, and the high voltage HEMT gate terminal are laterally spaced from one another; and wherein the transistor device first terminal and the transistor device second terminal are vertically spaced from one another.
Claims 9 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Korner in view of Vielemeyer et al.
Regarding claim 9, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above except for the high voltage transistor device and the transistor device comprises a superjunction, although Korner in view of Vielemeyer uses HEMT/MOSFET transistors instead of superjunction transistors for high voltage transistor device and the transistor device, these are just different types of transistors and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Regarding claim 13, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer further discloses wherein: the semiconductor switch is configured to turn-on or be in an on-state when the control terminal is driven with a peak voltage of [7 V, par. 0039]; and wherein the semiconductor switch is configured to turn-off or be in an off-state when the control terminal is driven with a minimum voltage of 0 V or negative [-5V, par. 0039], or with a voltage of less than a lower of: a threshold voltage of the high voltage HEMT; and a threshold voltage of the high voltage transistor device. Korner in view of Vielemeyer does not explicitly disclose a peak voltage of 10 V or more. One of ordinary skill in the art would have been motivated to have used the claimed range since such a voltage range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 14, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above except for the semiconductor switch comprises multiple high voltage HEMTs in parallel with one or more high voltage transistor devices; or multiple III-nitride integrated circuits in parallel with one or more high voltage transistor devices. It would have been obvious to one of ordinary skill in the art at the time the invention was made to have multiple high voltage HEMTs in parallel with one or more high voltage transistor devices; or multiple III-nitride integrated circuits in parallel with one or more high voltage transistor devices, since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 15, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above except for the semiconductor switch comprises a series combination of two or more III- nitride high voltage HEMTs in parallel with one or more high voltage transistor devices; or a series combination of two or more III -nitride integrated circuits connected in parallel with one or more high voltage transistor devices. It would have been obvious to one of ordinary skill in the art at the time the invention was made to have a series combination of two or more III-nitride high voltage HEMTs in parallel with one or more high voltage transistor devices; or a series combination of two or more III-nitride integrated circuits connected in parallel with one or more high voltage transistor devices, since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Korner in view of Vielemeyer et al. further in view of Lin et al. (US 2020/0105741 and Lin hereinafter).
Regarding claim 2, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer does not explicitly disclose wherein the interface circuit is partly disposed on a silicon circuit separate from the III-nitride integrated circuit.
However, Lin discloses [figs. 3A-3B] wherein interface circuit [306] is partly disposed on a silicon circuit [314a] separate from III-nitride integrated circuit [304]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner in view of Vielemeyer as taught in Lin in order to prevent leakage between the transistor devices [par. 34].
Regarding claim 11, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer does not explicitly disclose wherein the high voltage HEMT is disposed on a first semiconductor substrate, and wherein the high voltage transistor device is disposed on a second semiconductor substrate, different from the first semiconductor substrate.
However, Lin discloses [figs. 3A-3B] wherein HEMT [302] is disposed on a first semiconductor substrate [308a], and wherein high voltage transistor device [304] is disposed on a second semiconductor substrate [308b], different from the first semiconductor substrate. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner in view of Vielemeyer by incorporating different semiconductor substrate as taught in Lin in order to prevent leakage between the HEMT device and the transistor device [par. 34].
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Korner in view of Vielemeyer et al. further in view of Nair et al. (US 5939941 and Nair hereinafter).
Regarding claim 22, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer does not explicitly disclose wherein the high voltage HEMT source terminal and the transistor device first terminal are electrically connected to the first main terminal via a first passive component; and/or wherein the high voltage HEMT drain terminal and the transistor device second terminal are electrically connected to the second main terminal via a second passive component.
However, Nair discloses [see fig. 5] wherein a field effect transistor (FET) [55] and the transistor device [50] first terminal are electrically connected to first main terminal [VDD terminal] via a first passive component [58]; and/or wherein the high voltage FET drain terminal and the transistor device second terminal are electrically connected to second main terminal via a second passive component. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner in view of Vielemeyer by incorporating the passive component in order to improve high efficiency of the circuit.
Claims 12 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Korner in view of Vielemeyer et al. further in view of Udrea et al. (US 2020/0357907 and Udrea907 hereinafter).
Regarding claim 12, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer does not explicitly disclose wherein the high voltage HEMT and the low voltage auxiliary HEMT are disposed on a same semiconductor substrate.
However, Udrea907 discloses [see figs. 3-4] wherein a transistor [19, fig. 3] and transistor [16, fig. 3] are disposed on a same semiconductor substrate [4, fig. 4]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner in view of Vielemeyer by incorporating the high voltage HEMT and the low voltage auxiliary HEMT disposed on same semiconductor substrate as taught in Udrea907 in order to in order to have a one-piece, compact construction.
Regarding claim 24, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer does not explicitly disclose wherein the III-nitride integrated circuit and the high voltage transistor device are disposed in a singular package.
However, Udrea907 discloses [see figs. 3-4] wherein a transistor [19, fig. 3] and transistor [16, fig. 3] are disposed on a same semiconductor substrate [4, fig. 4]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner in view of Vielemeyer by incorporating the III-nitride integrated circuit and the high voltage transistor device disposed in a singular package as taught in Udrea907 in order to in order to have a one-piece, compact construction.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Korner in view of Vielemeyer further in view of Udrea et al. (WO 2020/225362).
Regarding claim 25, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer does not explicitly disclose wherein the interface circuit comprises: a low voltage auxiliary HEMT, the low voltage auxiliary HEMT comprising an auxiliary HEMT source terminal, an auxiliary HEMT drain terminal, and an auxiliary HEMT gate terminal; and a voltage limiter operatively connected to the auxiliary HEMT gate terminal; wherein the auxiliary HEMT source terminal is operatively connected to the high voltage HEMT gate terminal; wherein the auxiliary HEMT drain terminal is operatively connected to the control terminal; and wherein the voltage limiter is operatively connected to the high voltage HEMT source terminal and to the auxiliary HEMT gate terminal, further wherein the voltage limiter is configurable to limit a voltage across the high voltage HEMT gate terminal and the high voltage HEMT source terminal.
However, Udrea discloses [fig. 27] wherein the interface circuit [510c, see fig. 27] comprises: a low voltage auxiliary HEMT [transistor in 510c], the low voltage auxiliary HEMT comprising an auxiliary HEMT source terminal [510c terminal connected to 500], an auxiliary HEMT drain terminal [510c terminal connected to outside node], and an auxiliary HEMT gate terminal [gate 510c]; and a voltage limiter [520c] operatively connected to the auxiliary HEMT gate terminal; wherein the auxiliary HEMT source terminal is operatively connected to a voltage gate terminal [gate 500]; wherein the auxiliary HEMT drain terminal is operatively connected to a control terminal [external gate terminal]; and wherein the voltage limiter is operatively connected to the voltage source terminal and to the auxiliary HEMT gate terminal, further wherein the voltage limiter is configurable to limit a voltage across the voltage HEMT gate terminal and the high voltage HEMT source terminal [page. 39]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner in view of Vielemeyer by incorporating an interface circuit as taught in Udrea in order to protect the circuit from an over-current event.
Regarding claim 5, Korner in view of Vielemeyer discloses all the features with respect to claim 1 as indicated above. Korner in view of Vielemeyer does not explicitly disclose wherein the auxiliary HEMT drain terminal is operatively connected to the control terminal via a first resistance, and wherein the transistor device gate terminal is operatively connected to the control terminal via a second resistance.
However, Udrea discloses [fig. 27] disclose wherein the auxiliary HEMT drain terminal [510c terminal connected to outside node] is operatively connected to the control terminal via a first resistance [530a], and wherein the transistor device gate terminal [520a] is operatively connected to the control terminal via a second resistance [resistor in 520a]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Korner in view of Vielemeyer by incorporating the invention as taught in Udrea in order to protect the circuit from an over-current event.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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