DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendment, filed January 12, 2026, with respect to the rejections of claims have been fully considered. Applicant's amendment necessitated the new grounds of rejection presented below by using the reference of Khlat et al (US 2020/0295710).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7 – 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 2020/0228063) in view of Khlat et al (US 2020/0295710) (Khlat(2)).
Re claims 1, 10 and 20, Khlat teaches of a distributed power management circuit comprising: a plurality of distributed power management integrated circuits (PMICs) (#14, #74, DETIC, Fig.4) each configured to generate a respective one of a plurality of distributed voltages (VDCD, VCCD, Fig.4) based on a respective one of a plurality of distributed target voltages (VTGTD, VTGTD2, Fig.4); and a main PMIC (ETIC, Fig.4) comprising: a plurality of voltage circuits (a plurality of tracker/voltage circuits (#42, 38A, 22A and 96, 22B and 38B), Fig.4) each configured to generate a respective one of a plurality of voltages (VCCA and VCCB, Figures 2A, 2B and 4) and a respective one of a plurality of low-frequency currents (IDCA, IDCB, IDCD, IDCD2, Fig.4) based on a respective one of a plurality of target voltages (VTGA, VTGB Fig.4); and a control circuit (controller, #72, Fig.4) configured to: determine that at least two selected distributed PMICs (#14 and #74, Fig.4) among the plurality of distributed PMICs are needed to concurrently generate at least two distributed voltages among the plurality of distributed voltages (Paragraph 0046); cause at least two selected voltage circuits (MCP from each tracker circuit, Figures 1 and 2B) among the plurality of voltage circuits to each generate exclusively the respective one of the plurality of low-frequency currents (IDCD, IDCD2, Fig.4); and couple each of the at least two selected voltage circuits (MCP, Fig.2B) to a respective one of the at least two selected distributed PMICs to thereby provide the respective one of the plurality of low-frequency currents (IDCD, IDCD2, Fig.4) to the respective one of the at least two selected distributed PMICs (#14 and #74, Fig.4). However, Khlat does not specifically show each of the plurality of tracker/voltage circuits (#42, 38A, 22A and 96, 22B and 38B) being single voltage circuits. Khlat does not specifically teach of the main PMIC comprising: the plurality of voltage circuits greater in number than the plurality of distributed PMICs.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the tracker, auxiliary and voltage circuits integrated into a single voltage circuit, since it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
Khlat(2) teaches of a main PMIC (#12, Fig.1) comprising: the plurality of voltage circuits (#36A – #36B, Fig.1) greater in number than the plurality of distributed PMICs (single DETIC, Fig.1) (Paragraphs 0040 – 0041).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage circuits to be greater in number than the plurality of distributed PMICs so as to allow selection of voltages according to the operating mode.
Re claim 7, Khlat teaches of wherein each of the plurality of distributed PMICs comprises: a distributed voltage amplifier (#32, Fig.2A) configured to generate a respective distributed initial voltage (VAMP, Fig.2A) based on the respective one of the plurality of distributed target voltages (VTGT, Fig.2A); and a distributed offset capacitor (#34, Fig.2A) configured to raise the respective distributed initial voltage by a respective distributed offset voltage to generate the respective one of the plurality of distributed voltages (Paragraph 0029).
Re claim 8, Khlat and Khlat(2) teach all the limitations of claim 1 as well as Khlat(2) teaches of the plurality of distributed amplifiers are integrated into a single distributed PCB (Paragraph 0050).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of distributed PMICs be integrated into a single distributed PMIC for reduced size, enhanced quality control and cost efficiency.
Re claim 9, Khlat teaches of wherein the plurality of voltages comprises a mixture of envelope tracking (ET) (ET voltages VCCA and VCCB, Paragraph 0025) and average power tracking (APT) voltages (APT, Paragraph 0038).
Claims 2 – 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat and Khlat(2) in view of Khlat (US 2019/0238095) (Khlat(3)).
Re claims 2 and 11, Khlat and Khlat(2) teach all the limitations of claims 1 and 10 as well as Khlat teaches of the main PMIC is further configured to couple each of the plurality of voltage circuits to any one of a first set of voltage outputs (VCC, #16A, #16B, Fig.4) and a second set of voltage outputs (VDC, #40, #94, Fig.4), wherein: each of the first set of voltage outputs is coupled to a respective one of a plurality of main power amplifier circuits (#18A, #18B, Fig.4); and each of the second set of voltage outputs is coupled to a respective one of the plurality of distributed PMICs (#14, #74, Fig.4). Khlat(2) further teaches of an output switch circuit (#38, Figures 1 – 3) configured to couple each of the plurality of voltage circuits to a respective one of a plurality of main power amplifier circuits (#14, #16, Fig.1); and a voltage output is coupled to a distributed PMICs (#60, Fig.1). However, Khlat and Khlat(2) do not specifically teach of wherein the main PMIC further comprises: an input switch circuit coupled to the plurality of distributed PMICs and the plurality of voltage circuits and configured to receive the plurality of target voltages from a transceiver circuit.
Khlat(3) teaches of a PMIC that comprises: an input switch circuit (#28, Fig.3) coupled to a plurality of amplifiers (#34, Fig.3) and a voltage circuit (#18, Fig.3) and configured to receive the plurality of target voltages (#14(1) – #14(k), Fig.3) from a transceiver circuit (#38, Fig.3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an input switch circuit configured to receive the plurality of target voltages and selectively couple the target voltages to a respective circuit for synchronous operation. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have received the plurality of target voltages from a transceiver circuit to concurrently support a number of different wireless communication technologies. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an output switch circuit configured to couple each of the voltage outputs to a respective circuit to enable synchronous communication.
Re claim 3, Khlat, Khlat(2) and Khlat(3) teach all the limitations of claim 2 as well as Khlat further teaches of couple at least two selected voltage circuits to at least two of the second set of voltage outputs (#40, #94, Fig.4) that are coupled respectively to the at least two selected distributed PMICs (#14, #74, Fig.4). Khlat(2) further teaches of wherein the control circuit (#40, Fig.1) is further configured to control the output switch circuit (#38, Figures 1 – 2) to couple the at least two selected voltage circuits (as shown in Figures 1 – 2) to a voltage output (VDCD, Figures 1 – 2) that is coupled a distributed PMIC (#18, Figures 1 – 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the control circuit further configured to control the output switch circuit to perform synchronous operation on the voltage outputs.
Re claim 4, Khlat, Khlat(2) and Khlat(3) teach all the limitations of claim 2 as well as Khlat teaches of providing at least two of the plurality of target voltages to the at least two selected distributed PMICs as at least two of the plurality of distributed target voltages (VTGDT, VTGDT2, Fig.4). Khlat(3) further teaches of wherein the control circuit (#24, Fig.3) is further configured to control the input switch circuit (#28, Fig.3) to provide at least two of the plurality of target voltages (#14(1) - #14(k), Fig.3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the control circuit further configured to effectively control the operation of the input switch circuit.
Re claim 5, Khlat, Khlat(2) and Khlat(3) teach all the limitations of claim 4 as well as Khlat teaches of providing at least two of the plurality of target voltages to the at least two selected voltage circuits among the plurality of voltage circuits (VTGA, VTGB, Fig.3). Khlat(3) further teaches of wherein the control circuit (#24, Fig.3) is further configured to control the input switch circuit (#28, Fig.3) to provide at least two of the plurality of target voltages (#14(1) - #14(k), Fig.3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the control circuit further configured to effectively control the operation of the input switch circuit.
Re claim 6, Khlat, Khlat(2) and Khlat(3) teach all the limitations of claim 2 as well as Khlat teaches of wherein the control circuit is further configured to: cause at least one other voltage circuit among the plurality of voltage circuits (additional DETICs… to support more than one DETIC), which is different from the at least two selected voltage circuits, to generate concurrently the respective one of the plurality of voltages (a corresponding VDCD, Fig.4) and the respective one of the plurality of low-frequency currents (a corresponding IDCD, Fig.4); and couple the at least one other voltage circuit to at least one of the first set of voltage outputs (VDCD, Figures 2B and 4). Khlat(2) further teaches of controlling (#40, Fig.1) the output switch circuit (#38, Figures 1 – 2) to couple a voltage circuit to a voltage output (VDCD, Figures 1 – 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the control circuit further configured to control the output switch circuit to perform synchronous operation on the voltage outputs.
Claims 12 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat, Khlat(2)) and Khlat(3) in view of Khlat (US 2020/0343859) (Khlat(4)).
Re claim 12, Khlat, Khlat(2) and Khlat(3) teach all the limitations of claim 11 as well as Khlat further teaches of a set of main power amplifier circuits (#18A, #18B, Fig.4) each coupled to a respective one of the first set of voltage outputs (#22A, #22B, Fig.4); a set of distributed power amplifier circuits (#56, #24 and #58, 78, Fig.4) each coupled to a respective one of the plurality of distributed PMICs (#14, #74, Fig.4). Khlat(2) further teaches of a set of main power amplifier circuits (#14, #16, Fig.1) each coupled to a respective set of voltage outputs (#36A, #36B, Fig.1); a main antenna coupled to a respective one of the set of main power amplifier circuits (#80, Fig.4 and Paragraph 0052); a set of distributed power amplifier circuits (#62, #64, Fig.1) coupled to a distributed PMIC (#60, Fig.1); and a distributed antenna coupled to a respective one of the set of distributed power amplifier circuits (#78, Fig.4 and Paragraph 0052). Khlat, Khlat(2) and Khlat(3) do not specifically teach of the main antenna and distributed antenna each being a plurality of antennas.
Khlat(4) teaches of two sets of amplifier circuits, where each set is coupled to a number of antennas in an antenna array (Fig.1 and Paragraphs 0019 – 0020).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an antenna coupled to a respective one of the set of power amplifier circuits to enable wireless communication. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a plurality of antennas for each set of amplifier circuits for better signal strength and higher throughput.
Re claim 13, Khlat, Khlat(2), Khlat(3) and Khlat(4) teach all the limitations of claim 12 as well as Khlat(2) teaches of wherein: the main antenna (multiple antennas as taught above by Khlat(4)) is provided on an bottom edge of the wireless device (#80, Fig.4); and the distributed antenna (multiple antennas as taught above by Khlat(4)) is provided on a upper edge of the wireless device (#78, Fig.4). However, Khlat, Khlat(2), Khlat(3) and Khlat(4) do not show of the reverse order of placing the antennas.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the multiple main antennas provided on an upper edge of the wireless device and the multiple distributed antennas provided on a bottom edge of the wireless device, since it has been held that rearranging parts of an invention involves routine skill in the art. In re Japikse, 86 USPQ 70.
Re claim 14, Khlat, Khlat(2), Khlat(3) and Khlat(4) teach all the limitations of claim 12 as well as Khlat(2) further teaches of wherein: the set of main power amplifier circuits are located closer to the main antenna than to the distributed antenna (multiple antennas as taught above by Khlat(4)) (as shown in Figures 3B and 4); and the set of distributed power amplifier circuits are located closer to the distributed antenna than to the main antenna (multiple antennas as taught above by Khlat(4)) (as shown in Figures 3B and 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each circuit that include the set of power amplifier circuits located closer to antennas than to the antennas of a different circuit for improved system performance.
Re claim 15, Khlat, Khlat(2), Khlat(3) and Khlat(4) teach all the limitations of claim 12 as well as Khlat(4) further configuring to simultaneously transmit multiple first radio frequency (RF) signals via the first antennas (Paragraph 0019, Fig.1) and multiple second RF signals via the second antennas (Paragraph 0023, Fig.1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have configured to simultaneously transmit multiple first radio frequency (RF) signals via the multiple main antennas and multiple second RF signals via the multiple distributed antennas to increase data rates and enhance overall system capacity.
Re claim 16, Khlat, Khlat(2), Khlat(3) and Khlat(4) teach all the limitations of claim 15 as well as Khlat(4) teaches of simultaneously transmitting the multiple first RF signals and the multiple second RF signals via MIMO and RF beamforming (Paragraph 0019).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have simultaneously transmitted the multiple first RF signals and the multiple second RF signals via multiple-input multiple-output (MIMO) and RF beamforming for reduced interference and improved spectral efficiency.
Re claim 17, Khlat, Khlat(2), Khlat(3) and Khlat(4) teach all the limitations of claim 15 as well as Khlat further teaches of the system being capable of operating under 4G wireless technology and 5G wireless technology (Paragraph 0003).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the system configured to simultaneously transmit the multiple first RF signals based on fourth generation (4G) wireless technology and the multiple second RF signals based on fifth generation (5G) wireless technology so as to enable the capability to support connectivity for more devices on a network.
Re claim 18, Khlat, Khlat(2), Khlat(3) and Khlat(4) teach all the limitations of claim 12 as well as Khlat(4) teaches of simultaneously transmitting multiple first radio frequency (RF) signals via the multiple main antennas when the multiple distributed antennas are blocked (Paragraphs 0036).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have simultaneously transmitted multiple first radio frequency (RF) signals via the multiple main antennas when the multiple distributed antennas are blocked so as to mitigate a so-called hand-blocking effect.
Re claim 19, Khlat, Khlat(2), Khlat(3) and Khlat(4) teach all the limitations of claim 12 as well as Khlat(4) teaches of simultaneously transmitting multiple second radio frequency (RF) signals via the multiple distributed antennas when the multiple main antennas are blocked (Paragraphs 0036).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have simultaneously transmitted multiple second radio frequency (RF) signals via the multiple distributed antennas when the multiple main antennas are blocked so as to mitigate a so-called hand-blocking effect.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ARISTOCRATIS FOTAKIS/
Primary Examiner, Art Unit 2633