DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on June 18, 2026, is acknowledged. The traversal is on the ground(s) that it would not be a significant burden on the office to search and examine each of the identified inventions. This is not found persuasive because the elected claims encompass materially different technical features, including analog bias-modulation circuitry and switch-based bias control, which require separate prior-art searches in different technical areas and thereby impose a serious search and examination burden.
The requirement is still deemed proper and is therefore made FINAL.
Claims 10, 11, 19, 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected election of species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on June 18, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 12-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1: The recitations “first direct-current bias current”, (line 10) and “second direct-current bias current”, (line 12), lack the articles necessary to provide proper antecedent basis for the later recitations of “the first direct-current bias current” and “the second direct-current bias current.” Correction is required by amending the initial recitations to read “a first direct-current bias current” and “a second direct-current bias current.”
Regarding claims 2, 4-9, 17, 18 depend from claim 1 and therefore incorporate the indefinite limitations of claim 1.
Regarding claim 3: The recitations “power supply voltage”, (lines 5-6), “first direct-current bias current”, (lines 8-9), and “second direct-current bias current”, (lines 10-11), lack the articles necessary to provide proper antecedent basis for the later recitations of “the power supply voltage”, “the first direct-current bias current,” and “the second direct-current bias current.” Correction is required by amending the initial recitations to read “a power supply voltage,” “a first direct-current bias current,” and “a second direct-current bias current.”
Regarding claim 12: The recitations “first direct-current bias current”, (lines 11-12) and “second direct-current bias current” lack the articles necessary to provide proper antecedent basis for the later recitations of “the first direct-current bias current” and “the second direct-current bias current”. Correction is required by amending the initial recitations to read “a first direct-current bias current” and “a second direct-current bias current.”
Regarding claims 13-16 depend from claim 12 and therefore incorporate the indefinite limitations of claim 12.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-9, 12, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sukemori (US 2021/0126600 A1) in view of Shimamoto et al. (US 2020/0119695 A1).
Regarding claim 1: Sukemori, Fig. 2, discloses a power amplifier circuit (50) comprising: a power supply terminal (collector supply terminal 87); a first amplifier transistor (Q1) that has a first terminal connected to the power supply terminal (collector supply terminal 87), a second terminal (emitter of Q1), and a first control terminal (base of Q1) and that performs power amplification to a radio-frequency input signal input (RFin 85/terminal 56) from the first control terminal (base of Q1) to output a radio-frequency signal (Pout) resulting from the power amplification from the first terminal; a first bias circuit (20) that outputs first direct-current bias current (IB1); a second bias circuit (30) that outputs second direct-current bias current (IB2).
However Sukemori does not teach a modulation circuit, wherein the first bias circuit includes a first transistor that has a third terminal, a fourth terminal, and a second control terminal and that supplies the first direct-current bias current from the fourth terminal to the first control terminal, wherein the modulation circuit includes a second transistor which has a fifth terminal, a sixth terminal, and a third control terminal and the sixth terminal of which is connected to the fourth terminal, a first resistive element connected between the fifth terminal and the power supply terminal, and a second resistive element connected between the third control terminal and the second control terminal, and wherein the second bias circuit includes a third transistor that has a seventh terminal, an eighth terminal, and a fourth control terminal and that supplies the second direct-current bias current from the eighth terminal to the first control terminal
Shimamoto, Fig. 3, does disclose a modulation circuit (adjustment circuit 70), wherein the first bias circuit (20) includes a first transistor (Q50) that has a third terminal (base of Q70), a fourth terminal (emitter of Q70), a second control terminal (base of Q60) and that supplies the first direct-current bias current (IB1) from the fourth terminal (emitter of Q70) to the first control terminal (base of Q1), wherein the modulation circuit (adjustment circuit 70) includes a second transistor (adjustment transistor Q70) which has a fifth terminal (collector of Q70), a sixth terminal (base of Q70), and a third control terminal (base of Q70 [0064]) and the sixth terminal (base of Q70) of which is connected to the fourth terminal (emitter of Q70), a first resistive element (variable resistor R71 ) connected between the fifth terminal (collector of Q70) and the power supply terminal (90), and a second resistive element (variable resistor R72) connected between the third control terminal (base of Q70) and the second control terminal (base of Q60 ), and wherein the second bias circuit (30) includes a third transistor (transistor Q60) that has a seventh terminal, an eighth terminal, and a fourth control terminal (emitter of Q70) and that supplies the second direct-current bias current (IB1) from the eighth terminal to the first control terminal (base of Q2).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Sukemori’s modulation/bias circuitry with the adjustment circuit of Shimamoto in order to provide adjustable bias current in response to a variable power-supply voltage, thereby improving gain dispersion control and amplifier operating characteristics (Shimamoto, paragraph [0004]-[0007]).
Regarding claim 7: Sukemori, Fig. 2, further discloses wherein the power amplifier circuit includes a plurality of amplifier transistors (Q1- power stage amplifier, Q2-driver-stage amplifier) that includes the first amplifier transistor (Q1) and that is cascade-connected to each other (paragraphs [0026], lines 1, 4-6; [0027], lines 1-2; [0029], lines 1-2).
Regarding claim 8: Sukemori, Fig. 2, further discloses, wherein the first amplifier transistor (Q1) is arranged at a last stage in the plurality of amplifier transistors (Q2 precedes Q1 and the output is taken after Q1).
Regarding claim 9: Sukemori, Fig. 2, further discloses, wherein the plurality of amplifier transistors ( Q1 and Q2) includes the first amplifier transistor (Q1), and a second amplifier transistor (Q2) arranged at a previous state of the first amplifier transistor, and wherein the modulation circuit (baseband section 90) and the second bias circuit ( 30 ) are connected on a path between an output terminal of the second amplifier transistor (Q2) and an input terminal of the first amplifier transistor (Q1) in this order from the side closer to the second amplifier transistor (Q2).
Regarding claim 12: Sukemori, Fig. 2, discloses A power amplifier circuit (50) comprising: a power supply terminal (collector supply terminal 87); a first amplifier transistor (Q1) that has a first terminal connected to the power supply terminal (collector supply terminal 87), a second terminal (emitter of Q1), and a first control terminal (base of Q1) and that performs power amplification to a radio-frequency input signal input (RFin 85/terminal 56 ) from the first control terminal (base of Q1) to output a radio-frequency signal (Pout) resulting from the power amplification from the first terminal; a first bias circuit (20) that outputs first direct-current bias current (IB1).
However Sukemori does not teach a modulation circuit, wherein the first bias circuit includes a first transistor that has a third terminal, a fourth terminal, and a second control terminal and that supplies the first direct-current bias current from the fourth terminal to the first control terminal, wherein the modulation circuit includes a second transistor which has a fifth terminal, a sixth terminal, and a third control terminal and the sixth terminal of which is connected to the fourth terminal, a first resistive element connected between the fifth terminal and the power supply terminal, and a second resistive element connected between the third control terminal and the second control terminal, and wherein the second bias circuit includes a third transistor that has a seventh terminal, an eighth terminal, and a fourth control terminal and that supplies the second direct-current bias current from the eighth terminal to the first control terminal.
Shimamoto, Fig. 3, does disclose a modulation circuit (adjustment circuit 70), wherein the first bias circuit (20) includes a first transistor (Q50) that has a third terminal (base of Q70), a fourth terminal (emitter of Q70), a second control terminal (base of Q60) and that supplies the first direct-current bias current (IB1) from the fourth terminal (emitter of Q70) to the first control terminal (base of Q1), wherein the modulation circuit (adjustment circuit 70) includes a second transistor (adjustment transistor Q70) which has a fifth terminal (collector of Q70), a sixth terminal (base of Q70), and a third control terminal (base of Q70 [0064]), a first resistive element (variable resistor R71 ) connected between the fifth terminal (collector of Q70) and the power supply terminal (90), and a second resistive element (variable resistor R72) connected between the third control terminal (base of Q70) and the second control terminal (base of Q60 ), and a first switch (Sw11) paragraph [0090] which has a seventh terminal and an eighth terminal, the seventh terminal of which is connected to the sixth terminal, and the eighth terminal of which is connected to the fourth terminal.
It would have been obvious to one of having ordinary skill in the art at the time the invention
was effectively filed to incorporate Shimamoto’s switch arrangement into Sukemori’s bias/modulation circuitry to provide selectable operating modes through switch-controlled adjustment of the bias network.
Regarding claim 17: Sukemori further discloses he communication device (paragraph [0002] line 2-3) a comprising: a signal processing circuit that processes a radio-frequency signal (RF); and the power amplifier circuit (50) which transmits the radio-frequency signal between the signal processing circuit and an antenna (paragraph [0063] lines 2-6).
Regarding claim 18: Sukemori further discloses a power supply circuit (94) that supplies power supply voltage (Vreg) to the power amplifier circuit (paragraph [0059]-[0060]), wherein the power supply circuit (94) includes a power supply control circuit that controls the power supply voltage (Vcc1).
However, Sukemori does not disclose the power supply voltage (Vcc1) so as to be a linear function of power amplitude of the radio-frequency signal.
Shimamoto does disclose the power supply voltage (Vcc1) so as to be a linear function of power amplitude of the radio-frequency signal (RF) (paragraph [0049], lines 1-3; [0055]).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Sukemori’s power supply control using Shimamoto’s high-linearity control technique in order to improve the linearity of the power amplifier while maintaining desirable amplifier performance, as taught by Shimamoto.
Claims 2, 4, 5, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sukemori (US 2021/0126600 A1) in view of Shimamoto et al. (US 2020/0119695 A1) as applied to claim 1 above, in further view of Hitomi et al. (US 2020/0412306 A1).
Regarding claim 2: Sukemori as modified by Shimamoto does not disclose a control circuit that switches between the supply of the first direct-current bias current to the first control terminal and the supply of the second direct-current bias current to the first control terminal in accordance with a channel bandwidth of the radio-frequency input signal.
Hitomi, Fig. 5, does teach a control circuit (baseband section 90) that switches between the supply of the first direct-current bias current (IB1) to the first control terminal (base of Q2) and the supply of the second direct-current bias current (IB2) to the first control terminal (base of Q1) in accordance with a channel bandwidth (BW1/BW2) of the radio-frequency input signal (RFin 85/terminal 56).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to Sukemori and Shimamoto combination with Hitomi’s channel-bandwidth-based control so that the appropriate bias current is automatically selected according to the bandwidth of the radio-frequency input signal, thereby improving amplifier operation under different communication conditions while accommodating multiple operating modes.
Regarding claim 4: Sukemori, Fig. 2, further discloses an analog envelope tracking mode (paragraphs [0057], lines 3-6; [0061]-[0063]) in which the power supply voltage (Vreg) applied to the power supply terminal (collector supply terminal 87) is varied in a continuous voltage level in accordance with an envelope of the radio-frequency input signal (RFin 85/terminal 56), the control circuit causes the first bias circuit ( 20) to supply the first direct-current bias current (IB1) to the first amplifier transistor (Q1), and wherein, in an average power tracking mode in which the power supply voltage (Vreg) is varied in multiple discrete voltage levels in accordance with average output power of a radio-frequency signal (RFin 85/terminal 56), the control circuit causes the second bias circuit to supply the second direct current bias current to the first amplifier transistor (Q1).
Regarding claim 5: Sukemori as modified by Shimamoto does not disclose a first radio-frequency input signal of a first channel bandwidth and a second radio-frequency input signal of a second channel bandwidth wider than the first channel bandwidth are input into the first amplifier transistor, wherein, in a case that the first radio-frequency input signal is input into the first amplifier transistor, the control circuit causes the first bias circuit to supply the first direct-current bias current to the first amplifier transistor, and wherein, in a case that the second radio-frequency input signal is input into the first amplifier transistor, the control circuit causes the second bias circuit to supply the second direct-current bias current to the first amplifier transistor.
Hitomi, Fig. 5, does disclose a first radio-frequency input signal (Sig1) of a first channel bandwidth (BW1) and a second radio-frequency input signal ((sig2), paragraph [0060], lines 4-5) of a second channel bandwidth (BW2) wider than the first channel bandwidth ((BW1) paragraph [0022]), are input into the first amplifier transistor (Q1), wherein, in a case that the first radio frequency input signal (Sig1) is input into the first amplifier transistor (Q1), the control circuit (baseband section 90) causes the first bias circuit (20) to supply the first direct-current bias current (IB1) to the first amplifier transistor (Q1), and wherein, in a case that the second radio-frequency input signal (Sig2) is input into the first amplifier transistor (Q1), the control circuit (baseband section 90) causes the second bias circuit to supply the second direct-current bias current (IB2) to the first amplifier transistor (Q1).
It would have been obvious to one of having ordinary skill in the art at the time the invention
was effectively filed to modify the Sukemori and Shimamoto amplifier to utilize Hitomi’s bandwidth-dependent control because Hitomi teaches selecting ET or APT operation according to differing radio frequency channel bandwidths to reduce distortion while maintaining amplifier efficiency would have predictably adapted the combined amplifier to optimize operation for differing channel bandwidth conditions.
Regarding claim 6: Sukemori as modified by Shimamoto does not disclose a third radio-frequency input signal and a fourth radio-frequency input signal of a frequency band higher than that of the third radio-frequency input signal are input into the first amplifier transistor, wherein, in a case that the third radio-frequency input signal is input into the first amplifier transistor, the control circuit causes the first bias circuit to supply the first direct-current bias current to the first amplifier transistor, and wherein, in a case that the fourth radio-frequency input signal is input into the first amplifier transistor, the control circuit causes the second bias circuit to supply the second direct-current bias current to the first amplifier transistor.
Hitomi, fig. 1, discloses a third radio-frequency input signal (Sig1) and a fourth radio-frequency input signal (Sig2) (paragraph [0022], [0026]) of a frequency band higher than that of the third radio-frequency input signal are input into the first amplifier transistor (Q1), wherein, in a case that the third radio-frequency input signal ( Sig1 ) is input into the first amplifier transistor (Q1), the control circuit causes the first bias circuit (20) to supply the first direct-current bias current IB1)to the first amplifier transistor (Q1), and wherein, in a case that the fourth radio-frequency input signal (Sig2) is input into the first amplifier transistor (Q1), the control circuit causes the second bias circuit (30) to supply the second direct-current bias current (IB2) to the first amplifier transistor (Q1).
It would have been obvious to one of having ordinary skill in the art at the time the invention
was effectively filed to modify the combination of Sukemori and Shimamoto to configure the first amplifier transistor to receive RF input signals having differential bandwidths, as taught by Hitomi, so that the amplifier could selectively operate in the appropriate amplification mode for the particular RF signal, thereby improving operating efficiency and supporting operation across signals having different bandwidths.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sukemori (US 2021/0126600 A1) in view of Shimamoto et al. (US 2020/0119695 A1) in further view of Hitomi et al. (US 2020/0412306 A1).
Regarding claim 3: Sukemori, Fig. 2, discloses a power amplifier circuit comprising: a power supply terminal (collector supply terminal 87); a first amplifier transistor (Q1) to which power supply voltage (Vreg) is supplied from the power supply terminal (collector supply terminal 87) and which performs power amplification to a radio-frequency input signal (RFin 85/terminal 56 ); a first bias circuit (20) that supplies first direct-current bias current ( IB1) to the first amplifier transistor (Q1); a second bias circuit (30) that supplies second direct-current bias current (IB2) to the first amplifier transistor (Q1).
However, Sukemori does not teach a modulation circuit that is connected to the first bias circuit and the first amplifier transistor and that varies a magnitude of the first direct-current bias current in accordance with a magnitude of the power supply voltage; and a control circuit that switches between the supply of the first direct-current bias current to the first amplifier transistor and the supply of the second direct-current bias current to the first amplifier transistor in accordance with a channel bandwidth of the radio-frequency input signal.
Shimamoto discloses a modulation circuit (adjustment circuit 70 including transistor Q70) that is connected to the first bias circuit (20) and the first amplifier transistor (Q1) and that varies a magnitude of the first direct-current bias current (IB1) in accordance with a magnitude of the power supply voltage (Vreg).
However, Shimamoto does not teach a control circuit that switches between the supply of the first direct-current bias current to the first amplifier transistor and the supply of the second direct current bias current to the first amplifier transistor in accordance with a channel bandwidth of the radio-frequency input signal.
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to incorporate Shimamoto’s modulation circuit into Sukemori’s first bias circuit to provide supply-voltage-dependent adjustment of the first direct-current bias current, thereby improving amplifier operating characteristics under varying power-supply conditions, as taught by Shimamoto, (paragraph [0004]-[0007]).
Hitomi, Fig. 5, does teach a control circuit (baseband section 90) that switches between the supply of the first direct-current bias current (IB1) to the first amplifier transistor (Q1) and the supply of the second direct-current bias current (IB2) to the first amplifier transistor (Q1) in accordance with a channel bandwidth (BW1/BW2) of the radio-frequency input signal (RFin 85/terminal 56).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify Sukemori’s power amplifier by incorporating Shimamoto’s adjustment (modulation) circuit in order to adjust the magnitude of bias current according to the supplied power-supply voltage and thereby improve gain characteristics over varying operating conditions. It further would have been obvious to employ Hitomi’s baseband control to select between the first and second bias currents according to channel bandwidth because Hitomi teaches adapting amplifier operating characteristics based on transmission bandwidth, thereby further optimizing amplifier operation under varying RF conditions.
Claim 13-16 is rejected under 35 U.S.C. 103 as being unpatentable over Sukemori (US 2021/0126600 A1) in view of Shimamoto et al. (US 2020/0119695 A1) as applied to claim 12 above, in further view of Hitomi et al. (US 2020/0412306 A1).
Regarding claim 13: Sukemori as modified by Shimamoto does not disclose a control circuit that switches between connection between the seventh terminal and the eighth terminal and non-connection there between in accordance with a channel bandwidth of the radio-frequency input signal.
Hitomi, Fig. 5, does disclose a control circuit (baseband section 90) that switches between connection between the seventh terminal and the eighth terminal and non-connection there between in accordance with a channel bandwidth (BW1/BW2) of the radio-frequency input signal (Sig1)(paragraphs [0055], lines 3-7; [0056], lines 5-9; [0106], [0168], lines 8-12).
It would have been obvious to one of having ordinary skill in the art at the time the invention was effectively filed to modify the combination of Sukemori and Shimamoto to further configure the switching operation according to the controller-based ET/APT operating mode selection taught by Hitomi, in order to selectively connect and disconnect the bias path based on the operating mode and channel bandwidth, thereby providing appropriate bias control, improving amplifier operating characteristics, and reducing signal distortion (paragraph [0169]).
Regarding claim 14: Sukemori as modified by Shimamoto does not disclose an analog envelope tracking mode in which the power supply voltage applied to the power supply terminal is varied in a continuous voltage level in accordance with an envelope of the radio-frequency input signal, the control circuit connects the seventh terminal to the eighth terminal, and wherein, in an average power tracking mode in which the power supply voltage is varied in multiple discrete voltage levels in accordance with average output power of a radio-frequency signal, the control circuit does not connect the seventh terminal to the eighth terminal.
Hitomi, fig. 5, an analog envelope tracking mode (Abstract) in which the power supply voltage (Vreg) applied to the power supply terminal (collector supply terminal 87 )is varied in a continuous voltage level in accordance with an envelope of the radio-frequency input signal (Sig1), the control circuit (70) connects the seventh terminal to the eighth terminal, and wherein, in an average power tracking mode (Abstract) in which the power supply voltage (Vreg) is varied in multiple discrete voltage levels in accordance with average output power of a radio-frequency signal, the control circuit does not connect the seventh terminal to the eighth terminal (paragraphs [0104], [0105]; [0111], lines 2-6).
It would have been obvious to one of having ordinary skill in the art at the time the invention
was effectively filed to modify the combination of Sukemori and Shimamoto to operate that switching structure according to the ET and APT operating modes taught by Hitomi so that the bias path is connected during ET operation and disconnected during APT operation, thereby providing appropriate bias control for the selected amplification mode, improving amplifier operating characteristics, and reducing signal distortion (paragraph 0112], lines 2-5).
Regarding claim 15: Sukemori as modified by Shimamoto does not disclose a first radio-frequency input signal of a first channel bandwidth and a second radio-frequency input signal of a second channel bandwidth wider than the first channel bandwidth are input into the first amplifier transistor, wherein, in a case that the first radio-frequency input signal is input into the first amplifier transistor, the control circuit connects the seventh terminal to the eighth terminal, and wherein, in a case that the second radio-frequency input signal is input into the first amplifier transistor, the control circuit does not connect the seventh terminal to the eighth terminal.
Hitomi, fig. 5, does disclose a first radio-frequency input signal (Sig1) of a first channel bandwidth (BW1) and a second radio-frequency input signal (Sig2) of a second channel bandwidth (BW2) wider than the first channel bandwidth (paragraph [0022]) are input into the first amplifier transistor (Q1), wherein, in a case that the first radio-frequency input signal (Sig1) is input into the first amplifier transistor (Q1), the control circuit ((baseband 90) connects the seventh terminal to the eighth terminal, and wherein, in a case that the second radio-frequency input signal (Sig2) is input into the first amplifier transistor (Q1), the control circuit (baseband 90) does not connect the seventh terminal to the eighth terminal (paragraphs [0112]; [0113]; [0026], lines, 2-6).
It would have been obvious to one of having ordinary skill in the art at the time the invention
was effectively filed to modify the combination of Sukemori and Shimamoto to control the switching operation according to the bandwidth-dependent ET/APT operating modes taught by Hitomi, such that signals of different channel bandwidths selectively establish or remove the bias connection, thereby providing appropriate bias control for differing signal conditions, improving amplifier operating characteristics, and reducing signal distortion (paragraph [0112], lines 2-5).
Regarding claim 16: Sukemori as modified by Shimamoto does not disclose a third radio-frequency input signal and a fourth radio-frequency input signal of a frequency band higher than that of the third radio-frequency input signal are input into the first amplifier transistor, wherein, in a case that the third radio-frequency input signal is input into the first amplifier transistor, the control circuit connects the seventh terminal to the eighth terminal, and wherein, in a case that the fourth radio-frequency input signal is input into the first amplifier transistor, the control circuit does not connect the seventh terminal to the eighth terminal.
Hitomi, fig. 5, teaches discloses a third radio-frequency input signal ( Sig1 ) and a fourth radio-frequency input signal ( Sig2) (paragraph [0022], [0026]) of a frequency band higher than that of the third radio-frequency input signal are input into the first amplifier transistor (Q1), wherein, in a case that the third radio-frequency input signal ( Sig1 ) is input into the first amplifier transistor (Q1), the control circuit connects the seventh terminal to the eighth terminal, and wherein, in a case that the fourth radio-frequency input signal (Sig2 ) is input into the first amplifier transistor (Q1), the control circuit the control circuit does not connect the seventh terminal to the eighth terminal.
It would have been obvious to one of having ordinary skill in the art at the time the invention
was effectively filed to modify the combination of Sukemori and Shimamoto to operate the switching arrangement according to different radio-frequency input signals having different frequency bands, as taught by Hitomi, so that the amplifier selectively operates in the appropriate amplification mode for the particular RF input signal, thereby improving operating efficiency and supporting operation across signals having different bandwidths.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
The prior art of record, including Chiron et al. (US 2018/0013465 A1) discloses a multi-mode RF power amplifier architecture having first and second bias signal generators and switching circuitry that selectively supplies bias signals to RF power amplifiers based on the operating mode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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NATASHA Y. MARANO
Examiner
Art Unit 2843
/JOHN W POOS/Primary Examiner, Art Unit 2843
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