Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 22 December 2023, U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, and 7 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim).
In regards to claim 1 (Wang) shows:
A layout correction method for a semiconductor device, comprising: receiving a design layout including at least a target layer and a reference layer; Wang [0037] and [0046] teach a computational lithography method that receives an IC design layout having an IC feature in a current layer disposed over an underlying layer, the current layer corresponding to the target layer and the underlying layer corresponding to the reference layer.
detecting target edges comprising target patterns in the target layer, and detecting reference edges comprising reference patterns in the reference layer; Wang [0053] and [0034] teach a target contour of an IC feature in the current (target) layer and features formed in the underlying (reference) layer, the edges of which are identified for correction.
generating segments by dissecting the target edges based on dissection points set for the target edges, wherein the dissection points comprise the dissection point; Wang [0054] and [0055] teach dissecting a target contour into discrete segments defined between dissection points.
determining respective movement amounts of segments having evaluation points comprising the evaluation point set on the segments by inputting a feature measured at the evaluation points to a layout correction model; Wang [0059] and [0062] teach a target placement model that receives feature information at target points, and, in model-based OPC, biases each segment based on a deviation at the target points between a target contour and a predicted contour.
generating a corrected layout by moving the segments based on the movement amount; Wang [0058] and [0061] teach generating an OPCed (corrected) layout by biasing and shifting the segments.
forming a mask based on the corrected layout. Wang [0066] teaches fabricating a mask using the OPCed IC design layout.
Wang differs from the claimed invention in that it does not explicitly disclose determining a dissection point in a section intersecting a space between reference patterns on a target edge having three or more intersecting reference edges, among the target edges; and setting an evaluation point at an intermediate point of a section intersecting a reference pattern among the reference patterns on a segment intersecting the reference pattern, among the segments.
Kim teaches determining a dissection point in a section intersecting a space between reference patterns on a target edge having three or more intersecting reference edges, among the target edges; Kim [0038] teaches setting a dissection point at an intersection of a target pattern edge and a line projected from a vertex of an adjacent pattern that is spaced within a reference distance, and Kim [0025] and [0036] teach setting such dissection points for a target pattern with respect to the plurality of surrounding neighboring patterns, whereby a target edge crossing three or more neighboring (reference) patterns receives a dissection point located in the space between those patterns.
Kim teaches setting an evaluation point at an intermediate point of a section intersecting a reference pattern among the reference patterns on a segment intersecting the reference pattern, among the segments; Kim [0046] teaches setting a dissection point at a center point of an edge, i.e., at an intermediate point of the section.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang and Kim to place the dissection and evaluation points on the target edges based on the geometry of and spaces between the neighboring reference patterns, with a reasonable expectation of success as both references address optical proximity correction of semiconductor design layouts.
In regards to claim 3 (Wang) does not show: wherein the determining a dissection point comprises setting an intermediate point of a section intersecting the space as the dissection point;
Kim teaches wherein the determining a dissection point comprises setting an intermediate point of a section intersecting the space as the dissection point; Kim [0046] teaches setting the center point of an edge of a pattern as the dissection point, i.e., an intermediate point of the section.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang and Kim to locate the dissection point at the intermediate point of the section, with a reasonable expectation of success as both references address optical proximity correction of design layouts.
In regards to claim 4 (Wang) does not show: wherein the determining a dissection point comprises determining the space between the reference patterns, based on a direction of the reference edges intersecting the target edge;
Kim teaches wherein the determining a dissection point comprises determining the space between the reference patterns, based on a direction of the reference edges intersecting the target edge; Kim [0038] and [0098] teach projecting a line perpendicular to an edge in a given direction from a neighboring pattern to locate the dissection point relative to the space between patterns, the division criterion including the direction of the circuit pattern.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang and Kim to determine the space between the reference patterns from the direction of the reference edges, with a reasonable expectation of success as both references address optical proximity correction of design layouts.
In regards to claim 7 (Wang) shows the method of claim 1:
wherein the reference layer has patterns that overlap patterns of the target layer in the semiconductor device in a direction perpendicular to a surface of the semiconductor device; Wang [0037] and [0040] teach that the underlying (reference) layer sits below the current (target) layer such that its areas correspond to and vertically underlie the target-layer areas, i.e., overlap in a direction perpendicular to the substrate surface.
In regards to claim 8 (Wang) shows the method of claim 1:
wherein the reference patterns comprise active patterns of the semiconductor device, and the target patterns comprise gate patterns of the semiconductor device; Wang [0053] teaches that the IC features to be corrected include an active region and a gate feature, and Wang [0037] and [0034] teach that the current (target) layer is patterned over an underlying (reference) layer having features formed therein, and Kim [0032] teaches that the layout patterns include active patterns corresponding to an active layer and gate patterns corresponding to a gate or metal layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang and Kim such that the reference-layer patterns are the active patterns and the target-layer patterns are the gate patterns, with a reasonable expectation of success as both references address optical proximity correction of semiconductor design layouts having active and gate patterns.
In regards to claim 9 (Wang) shows the method of claim 1:
wherein the generating segments comprises determining a target edge for which a dissection point is not set as a single segment; Wang [0054] and [0055] teach that a target contour is divided into discrete segments defined between dissection points, such that an edge portion having no intervening dissection point constitutes a single segment.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim) and US20200356011A1 (Su).
In regards to claim 2 (Wang modified by Kim) does not show: wherein the layout correction model comprises a model that was machine-learned based on data measured at measurement points that are at an intermediate point of a section intersecting a pattern of a reference layer on an edge of the target layer, for determining a design layout for learning and a post-formation layout for learning;
Su teaches wherein the layout correction model comprises a model that was machine-learned based on data measured at measurement points that are at an intermediate point of a section intersecting a pattern of a reference layer on an edge of the target layer, for determining a design layout for learning and a post-formation layout for learning; Su [0059], [0075], and [0095] teach generating a layout correction model by performing machine learning on measured training data of a design layout and corresponding benchmark data, and Wang [0027] and [0028] teach measuring critical-dimension data of the design layout and of the post-formation (after-develop and after-etch) layout that serves as the data on which the model is machine-learned.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Wang and Kim with Su to machine-learn the layout correction model from the design-layout and post-formation critical-dimension data measured as taught by Wang, with a reasonable expectation of success as the references address machine-learning-based correction of design layouts.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim) and US20180300434A1 (Hu).
In regards to claim 10 (Wang modified by Kim) does not show: wherein the determining the respective movement amounts of segments having evaluation points set on the segments comprises predicting a process variation of the design layout by inputting the feature into the layout correction model, and determining the respective movement amounts of the segments to compensate for the process variation;
Hu teaches wherein the determining the respective movement amounts of segments having evaluation points set on the segments comprises predicting a process variation of the design layout by inputting the feature into the layout correction model, and determining the respective movement amounts of the segments to compensate for the process variation; Hu [0042] teaches predicting a process variation of the design layout by generating a Process Variation Band for the patterns of the design layout, and Wang [0058] and [0061], as set forth above, teach determining the respective movement amounts of the segments by biasing and shifting the segments to compensate for the predicted process variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Wang and Kim with Hu to predict and compensate for a process variation, with a reasonable expectation of success as the references address correction of semiconductor layout patterning.
In regards to claim 11 (Wang) shows the method of claim 10:
wherein the feature comprises at least one of a critical dimension (CD), a distance from an adjacent pattern, or a pattern density in a region of a predetermined range; Wang [0047] teaches topographical information including a pattern density, and Wang [0027] and [0028] teach critical dimension (CD) information.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim) and US20180157161A1 (Mailfert).
In regards to claim 12 (Wang modified by Kim) does not show: wherein the determining the respective movement amounts of segments having evaluation points set on the segments comprises predicting an etch step difference of a post-formation layout corresponding to the design layout by inputting a critical dimension (CD) measured based on the evaluation points into the layout correction model, and determining the respective movement amounts of the segments to compensate for the etch step difference that was predicted;
Mailfert teaches wherein the determining the respective movement amounts of segments having evaluation points set on the segments comprises predicting an etch step difference of a post-formation layout corresponding to the design layout by inputting a critical dimension (CD) measured based on the evaluation points into the layout correction model, and determining the respective movement amounts of the segments to compensate for the etch step difference that was predicted; Mailfert [0193] and [0209] teach predicting an edge placement error and critical-dimension variation of a post-etch (post-formation) layout from CD-related features, and Mailfert [0202] teaches modifying the design layout to provide a proximity-corrected layout that compensates for the predicted etch-induced difference.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Wang and Kim with Mailfert to predict and compensate for an etch step difference from measured CDs, with a reasonable expectation of success as the references address etch-aware correction of design layouts.
Claims 13 – 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim) and US20200356011A1 (Su).
In regards to claim 13 (Wang) shows:
A layout correction method for a semiconductor device, comprising: measuring data at measurement points that are at an intermediate point of a section intersecting a reference pattern of a reference layer on a target edge of target layers, for determining a design layout and a post-formation layout; Wang [0027] and [0028] teach measuring critical-dimension data of the design layout and of the post-formation (after-develop and after-etch) layout at points on a target edge.
generating a corrected layout by applying data measured at evaluation points set by criteria consistent with the measurement points, for the segments, to the layout correction model; Wang [0059] and [0061] teach applying feature data at target/evaluation points to a placement model and biasing the segments to generate a corrected layout.
forming a mask based on the corrected layout. Wang [0066] teaches fabricating a mask using the corrected layout.
Wang differs from the claimed invention in that it does not explicitly disclose the measurement points being at an intermediate point of a section intersecting a reference pattern of a reference layer; generating a layout correction model by performing machine learning based on the data that was measured; and dissecting edges intersecting two or more reference patterns, among target edges including the target edge of a target layer among the target layers, into segments respectively intersecting one reference pattern of the two or more reference patterns.
Kim teaches the measurement points being at an intermediate point of a section intersecting a reference pattern of a reference layer, and dissecting edges intersecting two or more reference patterns into segments respectively intersecting one reference pattern of the two or more reference patterns; Kim [0046] teaches locating a point at the center (intermediate) point of a section of an edge, and Kim [0025], [0028], and [0038] teach dividing a target edge into segments based on the plurality of surrounding patterns such that the segments correspond to individual neighboring (reference) patterns.
Kim differs from the claimed invention in that it does not explicitly disclose generating a layout correction model by performing machine learning based on the data that was measured.
Su teaches generating a layout correction model by performing machine learning based on the data that was measured; Su [0059], [0075], and [0095] teach generating a machine-learning model for layout correction by training it on measured benchmark data.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang and Kim to measure data at the intermediate points of the sections crossing the reference patterns and dissect the target edges into segments corresponding to individual reference patterns, with a reasonable expectation of success as both references address optical proximity correction of design layouts.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Wang and Kim with Su to generate the layout correction model by performing machine learning on the measured data, with a reasonable expectation of success as the references address computational correction of design layouts.
In regards to claim 14 (Wang) shows the method of claim 13:
wherein the post-formation layout is an after-cleaning-inspection (ACI) layout or an after-develop-inspection (ADI) layout; Wang [0027] teaches an after development inspection (ADI) of the post-formation resist layout.
In regards to claim 15 (Wang) shows the method of claim 13:
wherein the data at measurement points comprises at least one of a critical dimension (CD), a distance between the measurement points and an adjacent pattern, or a pattern density in a region of a predetermined range from one or more of the measurement points; Wang [0027], [0028], and [0047] teach that the measured data includes critical dimension (CD) information and pattern density.
In regards to claim 18 (Wang) does not show: further comprising, in each of the segments, setting an evaluation point of the evaluation points at an intermediate point of a section intersecting a pattern of the reference layer;
Kim teaches further comprising, in each of the segments, setting an evaluation point of the evaluation points at an intermediate point of a section intersecting a pattern of the reference layer; Kim [0046] teaches setting a point at the center (intermediate) point of an edge of a pattern, i.e., at an intermediate point of the section.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang and Kim to set an evaluation point at the intermediate point of each section intersecting a reference pattern, with a reasonable expectation of success as both references address optical proximity correction of design layouts.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim), US20200356011A1 (Su), and US20170363950A1 (Sriraman).
In regards to claim 16 (Wang modified by Kim and Su) does not show: wherein the data at measurement points further comprises an etch step difference determined based on first CDs measured in the design layout and second CDs measured in the post-formation layout;
Sriraman teaches wherein the data at measurement points further comprises an etch step difference determined based on first CDs measured in the design layout and second CDs measured in the post-formation layout; Sriraman [0185] and [0189] teach determining an etch-induced difference based on CDs measured in the design layout and CDs measured in the post-etch (post-formation) layout.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Wang, Kim, and Su with Sriraman to include an etch step difference determined from design-layout and post-formation CDs, with a reasonable expectation of success as the references address etch-aware layout correction.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim), US20200356011A1 (Su), and US20180300434A1 (Hu).
In regards to claim 17 (Wang modified by Kim and Su) does not show: wherein the generating a corrected layout comprises predicting a process variation by applying data measured at the evaluation points to the layout correction model, and correcting a shape of a pattern of the target layers by moving the segments to compensate for the process variation that was predicted;
Hu teaches wherein the generating a corrected layout comprises predicting a process variation by applying data measured at the evaluation points to the layout correction model, and correcting a shape of a pattern of the target layers by moving the segments to compensate for the process variation that was predicted; Hu [0042] teaches predicting a process variation by generating a Process Variation Band for the patterns, and Wang [0058] and [0061], as set forth above, teach correcting a shape of a pattern by moving the segments to compensate for the predicted process variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Wang, Kim, and Su with Hu to predict a process variation and correct the pattern shape accordingly, with a reasonable expectation of success as the references address correction of semiconductor layout patterning.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim).
In regards to claim 19 (Wang) shows:
A mask manufacturing method for a semiconductor device, comprising: receiving a design layout including at least a target layer and a reference layer below the target layer; Wang [0037] and [0046] teach receiving an IC design layout having a current (target) layer and an underlying (reference) layer disposed below the target layer.
generating a corrected layout by applying respective features at evaluation points to a process proximity correction (PPC) model and by moving segments having the evaluation points according to a result of the applying; Wang [0059], [0061], and [0064] teach applying feature values at target/evaluation points to a process model and moving the segments accordingly to generate a corrected layout.
generating a mask layout by performing optical proximity correction (OPC) on the corrected layout; Wang [0019] and [0061] teach performing optical proximity correction to generate an OPCed mask layout.
manufacturing a mask based on the mask layout. Wang [0066] teaches fabricating a mask based on the OPCed layout.
Wang differs from the claimed invention in that it does not explicitly disclose generating segments by dissecting target edges of the target layer based on sections intersecting a space between reference patterns of the reference layer; and setting an evaluation point at an intermediate point of a intersecting section intersecting a reference pattern, in segments having the intersecting section, respectively, among the segments that were generated.
Kim teaches generating segments by dissecting target edges of the target layer based on sections intersecting a space between reference patterns of the reference layer, and setting an evaluation point at an intermediate point of a intersecting section intersecting a reference pattern, in segments having the intersecting section, respectively; Kim [0025], [0038], and [0028] teach dissecting target edges into segments based on the geometry of and spaces between the surrounding patterns, and Kim [0046] teaches setting the point at the intermediate (center) point of the section.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Wang and Kim to dissect the target edges based on the spaces between the reference-layer patterns and set the evaluation points at the intermediate points of the sections, with a reasonable expectation of success as both references address optical proximity correction of design layouts.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US20190094710A1 (Wang) in view of US20200081352A1 (Kim) and US20200356011A1 (Su).
In regards to claim 20 (Wang modified by Kim) does not show: wherein one or more of the evaluation points are set by criteria consistent with measurement points used in machine learning of the PPC model;
Su teaches wherein one or more of the evaluation points are set by criteria consistent with measurement points used in machine learning of the PPC model; Su [0075] and [0095] teach that the model is trained by machine learning on measurement data, such that the evaluation points at which data is applied are set consistent with the measurement points used to train the model.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Wang and Kim with Su to set the evaluation points consistent with the measurement points used to train the model, with a reasonable expectation of success as the references address machine-learning-based correction of design layouts.
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art of record does not teach or suggest "wherein the target edges and the reference edges have a direction of 0 degrees, 90 degrees, 180 degrees, or 270 degrees, ... wherein the determining the space between the reference patterns comprises, after setting a direction of the target edge as a reference direction, determining a space between a first reference edge among the reference edges having a direction of 270 degrees from the reference direction and a second reference edge among the reference edges adjacent to the first reference edge in the reference direction and having a direction of 90 degrees from the reference direction, as the space between the reference patterns" in combination with the other limitations of the claim.
Regarding claim 6, the prior art of record does not teach or suggest "wherein the setting an evaluation point comprises, after setting a direction of the segment as a reference direction, determining a space between a third reference edge among the reference edges having a direction of 90 degrees from the reference direction and a fourth reference edge among the reference edges adjacent to the third reference edge in the reference direction and having a direction of 270 degrees from the reference direction, as the section intersecting the reference pattern" in combination with the other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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