DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (hereinafter WANG) (US 2018/0107519 A1) in view of Zaykov et al. (hereinafter ZAYKOV) (US 2023/0305888 A1).
As to claim 1, WANG teaches a graphics processor (GPU) (Abstract), comprising:
to process multi-kernel in parallel (at least two SMs 102 capable of communicating with a global scheduler 101; kernel status register table 1012 includes a priority of each kernel program, to-be-distributed kernel program, etc.), wherein each processing partition comprises ([0051]; [0067]; Fig. 1):
a plurality of processing units, each processing unit comprising a computing unit (GPU system includes at least two SMs and the global scheduler 101 distributes kernel programs to SMs 102) (Fig. 1) and a storage block (thread block status register table 1022 and/or the SM status register table 1013, etc.) ([0053]; [0059]); and
processing a first kernel of the multi-kernel (to-be-distributed kernel is the highest-priority kernel with undistributed thread blocks) ([0066]-[0067]); and
processing a second kernel having a priority lower than a priority of the first kernel of the multi-kernel (selects a second SM where the highest priority of a thread block in that second SM is lower than the priority of the to-be-distributed kernel program) ([0078]-[0080]; Fig. 2);
a controller (Global logic controller 1011) configured to generate control information according to kernel priority information (information about the kernel program includes a priority of the kernel program) when workload corresponding to the first kernel meets a predetermined criterion (The SM capable of running at least one entire thread block is an SM in which a quantity of remaining registers is greater than a quantity of registers required for running a thread block, in which a quantity of remaining hardware warps is greater than a quantity of hardware warps required for running a thread block, and in which remaining shared memory space is greater than shared memory space required for running a thread block.), the control information indicating a donor (processes the lower-priority second kernel, etc.) (When the first SM is not found, the global logic controller searches for a second SM, where a highest priority of a thread block in the second SM is lower than a priority of the to-be-distributed kernel program) ([0051]; [0054]-[0058]; [0071]; [0078]; [0117]-[0121]); and
a dispatch module (first distribution unit 6013) coupled to the controller (Global logic controller), wherein the dispatched module is configured to (Fig. 6):
dispatch the first kernel (to-be-distributed kernel program is a kernel program whose priority is highest in the kernel status register table and in which a quantity of undistributed thread blocks is not zero) ([0067]); and
dispatch a thread block of the first kernel to a processing unit of the donor according to the control information when the workload meets the predetermined criterion (distributes a thread block from the high-priority to-be-distributed kernel program to the second SM, which is lower in priority) ([0079]-[0081]).
As shown above, WANG teaches that the system includes a global scheduler 101 and at least two SMs 102 capable of communicating with the global scheduler 101 and that the global scheduler 101 is configured to distribute a kernel program to the SM 102 for running ([0051]; [0054]). WANG further teaches selecting a second SM where a highest priority of a thread block in the second SM is lower than a priority of the to-be-distributed kernel program ([0078]).
However, WANG does not teach a multi-processing partition comprises a first processing partition for processing a first kernel and a second processing partition for processing a lower-priority second kernel. Instead, WANG teaches selection and distribution at the SM level.
ZAYKOV teaches a GPU/coprocessor architecture in which processing resources are partitioned and assigned to particular workloads/kernels, and that some coprocessors enable time and/or space partitioning of its processing resources so that multiple jobs can be executed in parallel, providing spatial isolation, time determinism, and responsiveness ([0006]; Figs 2A and 9). A workload is defined as a job, kernel, or shader and may be represented as kernels and include associated priorities ([0004]; [0035]). ZAYKOV also teaches GPU partitions, stating that the GPU is sliced into multiple GPU partitions, and that workloads from different CPU tasks are assigned to different GPU partitions ([0091]). Workload assignment considers workload priority and available partition resources, and that higher-priority workloads are generally assigned before lower-priority workloads and to more available clusters than the low-priority workload ([0093]). Therefore, ZAYKOV teaches a multi-processing partition comprises a first processing partition for processing a first kernel and a second processing partition for processing a lower-priority second kernel.
It would have been obvious to one of ordinary skill in the art before the effective date of the application to modify WANG’s priority-based GPU resource allocation system to include ZAYKOV’s teaching of a multi-processing partition comprises a first processing partition for processing a first kernel and a second processing partition for processing a lower-priority second kernel. The suggestion/motivation for doing so would have been to provide the predicted result of solving the problem of coprocessors becoming overwhelmed with backed up workload launch requests and reducing processing delays and loss of guarantees to determinism (ZAYKOV - [0005]-[0006]).
As to claim 2, WANG teaches the graphics processor according to claim 1, wherein the processing unit of the donor processing partition is a processing unit that is assigned to a thread block of the second kernel in the second processing partition ([0078]-[0080]).
As to claim 3, WANG ([0068]-[0071]) in view of ZAYKOV ([0119]) teaches the graphics processor according to claim 1, wherein the processing unit of the donor processing partition is a processing unit that is not assigned to a thread block of the second kernel in the second processing partition.
As to claim 4, WANG ([0003]) in view of ZAYKOV ([0053]) teaches the graphics processor according to claim 1, wherein the controller is configured to: estimate whether a delay time is greater than a predetermined time, the delay time caused by using the first processing partition to complete execution of the first kernel; and when the estimated delay time is greater than the predetermined time, determine that the workload of the first processing partition meets the predetermined criterion.
As to claim 5, WANG teaches the graphics processor according to claim 1, wherein the controller comprises: a partition management module configured to: select the first kernel according to the kernel priority information; and determine whether the workload of the first processing partition for executing the first kernel meets the predetermined criterion; and a control information generation module coupled to the partition management module, and configured to: generate the control information at least according to the kernel priority information when the workload of the first processing partition meets the predetermined criterion ([0115]-[0117]).
As to claim 6, WANG ([0078]-[0079]) in view of ZAYKOV ([0091]) teaches the graphics processor according to claim 5, wherein the control information further indicates that a first processing unit in the second processing partition is selected as the processing unit of the donor processing partition, and the control information generation module comprises: a donor partition selection module configured to select the second processing partition as the donor processing partition at least according to the kernel priority information; and a donor unit selection module coupled to the donor partition selection module, and configured to select the first processing unit of the second processing partition as the processing unit of the donor processing partition and generate the control information accordingly.
As to claim 7, WANG ([0084]-[0085]) in view of ZAYKOV ([0093]) teaches the graphics processor according to claim 6, wherein the multi-kernel comprises a third kernel having a priority equal to the priority of the second kernel, and the third kernel is dispatched to a third processing partition of the multi-processing partition; the donor partition selection module is further configured to: determine through calculation that a maximum number of thread blocks of the first kernel that can be dispatched to the second processing partition is greater than a maximum number of thread blocks of the first kernel that can be dispatched to the third processing partition according to kernel usage information, the kernel usage information indicating resources used to execute the first kernel; and select the second processing partition as the donor processing partition.
As to claim 8, WANG ([0059]-[0060]) in view of ZAYKOV ([0093]) teaches the graphics processor according to claim 6, wherein the donor unit selection module is configured to select the first processing unit of the second processing partition as the processing unit of the donor processing partition according to processing unit performance information, the processing unit performance information indicating that a weight of the first processing unit of the second processing partition is lower than a weight of another processing unit of the second processing partition in processing operation of the second kernel.
As to claim 9, WANG ([0057]-[0060]; [0090]) in view of ZAYKOV ([0080]) teaches the graphics processor according to claim 1, wherein the dispatch module is configured to: store processing unit allocation information that indicates a group of processing units of the first processing partition as a group of processing units for processing the first kernel; and update the processing unit allocation information according to the control information when the workload of the first processing partition meets the predetermined criterion, wherein the group of processing units for processing the first kernel comprises the processing unit of the donor processing partition.
As to claim 10, WANG ([0106]-[0107]; [0090]) in view of ZAYKOV ([0080]) teaches the graphics processor according to claim 9, wherein after execution of the first kernel is completed, the dispatch module is configured to reset the processing unit allocation information, and the group of processing units of the first processing partition serves as the group of processing units for processing the first kernel.
As to claim 11, WANG ([0099]-[0100]) in view of ZAYKOV ([0080]-[0081]) teaches the graphics processor according to claim 6, wherein when the first processing unit of the second processing partition is selected as the processing unit of the donor processing partition, the dispatch module is configured to stop dispatching the thread block of the second kernel to the first processing unit of the second processing partition.
As to claim 12, it is rejected for the same reasons as stated in the rejection of claim 1.
As to claim 13, it is rejected for the same reasons as stated in the rejection of claims 2-3.
As to claim 14, it is rejected for the same reasons as stated in the rejection of claim 4.
As to claim 15, it is rejected for the same reasons as stated in the rejection of claim 5.
As to claim 16, it is rejected for the same reasons as stated in the rejection of claim 7.
As to claim 17, it is rejected for the same reasons as stated in the rejection of claim 8.
As to claim 18, WANG ([0057]-[0060]; [0090]) in view of ZAYKOV ([0103]-[0105]) teaches the operation method according to claim 12, wherein dispatching the thread block of the first kernel to the processing unit of the donor processing partition further comprises: dispatching the thread block of the first kernel to the processing unit of the donor processing partition according to processing unit allocation information, the processing unit allocation information indicating that a group of processing units for processing the first kernel comprises the processing unit of the donor processing partition; wherein before the thread block of the first kernel is dispatched to the processing unit of the donor processing partition, the processing unit allocation information indicates that the group of processing units for processing the first kernel all come from the first processing partition.
As to claim 19, it is rejected for the same reasons as stated in the rejection of claim 10.
As to claim 20, WANG ([0099]-[0100]) in view of ZAYKOV ([0080]-[0081]) teaches the operation method according to claim 17, wherein when the first processing unit of the second processing partition is selected as the processing unit of the donor processing partition, the method further comprises: prohibiting dispatching the thread block of the second kernel to the first processing unit of the second processing partition.
Conclusion
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/KENNETH TANG/Primary Examiner, Art Unit 2197
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