DETAILED ACTION
Claim Objections
Claims 1, 8, 11, and 15-17 are objected to because of the following informalities:
Regarding claim 1, “the oxide layer” in line 11 should be changed to “the silicon oxide layer”.
Regarding claim 8, “wherein the wherein the” should be changed to “wherein the”.
Regarding claim 11, “the bonding surface a second dielectric layer” in lines 8-9 should be changed to “a bonding surface, a second dielectric layer”.
Regarding claim 15, “at least one second bonding pads” in line 6, “the first bonding pads and the second bonding pads…the first bonding pads to the second bonding pads” in lines 11-13, and “the first bonding pads” in line 24 should be changed to “at least one second bonding pad”, “the first bonding pad and the second bonding pad…the first bonding pad to the second bonding pad”, and “the first bonding pad”.
Regarding claim 16, “the first upper vertical expansion including layer” should be changed to “the first upper expansion including layer”.
Regarding claim 17, “the second bonding pads” in line 11 and “the first vertical expansion including layer” in line 15 should be changed to “the second bonding pad” and “the first upper expansion including layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, the limitation (1) “providing a second bonding structure including a second bonding insulation layer and at least one second bonding pads in the second bonding insulation layer over a first device layer; bonding the first bonding structure and the second bonding structure to make the first bonding insulation layer contact the second bonding insulation layer over a second device layer” in combination with the limitation (2) “wherein providing the first bonding structure includes: forming a first lower vertical expansion inducing layer over the first device laver” in claim 15 and “wherein providing the second bonding structure includes: forming a second lower vertical expansion inducing layer over the second device laver” in claim 17 would render the claim indefinite since the limitations (1) and (2) above appear to be conflicting with each other with respect to the first device layer and the second device layer. Specifically, the limitation (1) appears to be incorrectly specifying that the providing the second bonding structure is “over a first device layer” and the bonding step is “over a second device layer”. Claims 16-19, which depend from claim 15, are also rejected by virtue of their dependencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, 8, 11, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2021/0057371 A1; hereinafter “Park”).
Regarding claim 1, referring to Figs. 4-7, Park teaches a bonding structure comprising: a plurality of bonding pads (155) (paragraphs 31-32); and a bonding insulation layer (110, 120, and 130) configured to electrically isolate the bonding pads from each other (paragraphs 22-24); wherein the bonding insulation layer includes a first vertical expansion including layer (130) positioned at a bonding surface (a top surface of 130 facing 230 for bonding) (paragraph 24); a silicon oxide layer (120 formed of silicon oxyfluoride SiOF, which is a member of silicon oxide material) disposed under the first vertical expansion including layer (paragraph 23); and a second vertical expansion including layer (110) disposed under the oxide layer (paragraph 22); wherein the first vertical expansion inducing layer comprises a hardness greater than a hardness of the silicon oxide layer (130 formed of SiCN has a hardness/density greater than that of 120 formed of SiOF as material properties) (paragraphs 23-24).
Regarding claim 2, Park teaches wherein the second vertical expansion including layer comprises a hardness greater than the hardness of the silicon oxide layer (110 formed of TEOS has a hardness/density greater than that of 120 formed of SiOF as material properties) (paragraphs 22-23).
Regarding claim 4, Park teaches wherein the first vertical expansion inducing layer comprises a silicon nitride layer (130 formed of SiCN, which is a member of silicon nitride material) (paragraph 24).
Regarding claim 6, referring to Figs. 4-7, Park teaches a semiconductor device comprising: a first bonding structure including a first bonding layer (a bottom structure in Fig. 7 including at least 110, 120 and 130) (paragraphs 19-32); and a second bonding structure including a second bonding layer (a top structure in Fig. 7 including at least 210, 220, and 230) bonded to the first bonding layer (paragraphs 34-38 and 43-44); wherein at least one of the first bonding layer and the second bonding layer comprises: a plurality of bonding pads (155) (paragraphs 31-32); and a bonding insulation layer (110, 120, and 130) arranged between the bonding pads, the bonding insulation layer including an upper region (a region having 130) adjacent to a bonding surface between the first bonding layer and the second bonding layer, a middle region (a region having 120) under the upper region, and a lower region (a region having 110) under the middle region (paragraphs 22-24); and wherein an interface stress between the upper region of the bonding insulation layer and the bonding pad is greater than an interface stress between the middle region of the bonding insulation layer and the bonding pad (an interface stress between the region having 130 formed of SiCN and 155 is greater than an interface stress between the region having 120 formed of SiOF and 155) (paragraphs 23-24); wherein the upper region of the bonding insulation layer comprises a first dielectric material including silicon nitride material (130 formed of SiCN), the middle region of the bonding insulation layer comprises a second dielectric material including silicon oxide material (120 formed of SiOF), and the lower region of the bonding insulation layer comprises a third dielectric material (110 formed of TEOS) (paragraphs 22-24); and wherein a hardness of the first dielectric material is greater than a hardness of the second dielectric material (130 formed of SiCN has a hardness/density greater than that of 120 formed of SiOF as material properties) (paragraphs 23-24).
Regarding claim 8, Park teaches wherein the wherein the third dielectric material has a hardness greater than the hardness of the second dielectric material (110 formed of TEOS has a hardness/density greater than that of 120 formed of SiOF as material properties) (paragraphs 22-23).
Regarding claim 11, referring to Figs. 4-7, Park teaches a semiconductor device comprising: a device layer (a layer, not shown, including semiconductor elements such as transistors and capacitors, and wirings on 100) (paragraphs 20-21); and a bonding structure (a structure including at least 110, 120, and 130) formed over the device layer, the bonding structure comprising a bonding insulation layer (110, 120, and 130) and at least one bonding pad (155) formed in the bonding insulation layer; wherein the bonding insulation layer includes a first dielectric layer (130) adjacent to the bonding surface (a top surface of 130 facing 230 for bonding) a second dielectric layer (120) disposed under the first dielectric layer, and a third dielectric layer (110) disposed between the second dielectric layer and the device layer (paragraphs 21-23); wherein the first dielectric layer includes silicon nitride material (130 formed of SiCN), and the second dielectric layer includes silicon oxide material (120 formed of SiOF) (paragraphs 23-24).
Regarding claim 15, Park teaches a method of manufacturing a semiconductor device, the method comprising: providing a first bonding structure including a first bonding insulation layer (a structure including at least 110, 120, and 130) and at least one first bonding pad (155) in the first bonding insulation layer (Fig. 4 and paragraphs 19-32); providing a second bonding structure including a second bonding insulation layer (a structure including at least 210, 220, and 230) and at least one second bonding pads (255) in the second bonding insulation layer over a first device layer (a layer, not shown, including semiconductor elements such as transistors and capacitors, and wirings on 100) (Fig. 5 and paragraphs 20-21 and 34-38); bonding the first bonding structure and the second bonding structure to make the first bonding insulation layer contact the second bonding insulation layer over a second device layer (a layer, not shown, including semiconductor elements such as transistors and capacitors, and wirings on 200) (Fig. 6 and paragraphs 20-21, 34, and 39-42); and thermally expanding the first bonding pads and the second bonding pads in a vertical direction to hybrid-bond the first bonding pads to the second bonding pads (Fig. 7 and paragraphs 43-45); wherein providing the first bonding structure includes: forming a first lower vertical expansion including layer (110) over the first device layer (paragraph 22); forming at least one first buffer layer including silicon oxide material (120 formed of SiOF) on the first lower vertical expansion including layer (paragraph 23); forming a first upper expansion including layer (130) on the first buffer layer, the first upper expansion including layer directly contacting the second bonding structure (Fig. 6), and the first upper vertical expansion including layer including silicon nitride material (130 formed of SiCN) (paragraph 24); and forming the first bonding pads through the first upper vertical expansion inducing layer, the first buffer layer, and the first lower vertical expansion including layer (Fig. 4 and paragraphs 31-32).
Regarding claim 17, Park teaches wherein providing the second bonding structure includes: forming a second lower vertical expansion including layer (210) over the second device layer (Figs. 1-5 and paragraphs 34-38); forming at least one second buffer layer including silicon oxide material (220 formed of SiOF), on the second lower vertical expansion including layer (Figs. 1-5 and paragraphs 34-38); forming a second upper vertical expansion inducing layer (230) on the second buffer layer (Figs. 1-5 and paragraphs 34-38), the second upper vertical expansion inducing layer including silicon nitride material (230 formed of SiCN) (Figs. 1-5 and paragraphs 34-38); and forming the second bonding pads (255) through the second upper vertical expansion inducing layer, the second buffer layer, and the second lower vertical expansion including layer (Figs. 1-5 and paragraphs 34-38); wherein the second upper vertical expansion inducing layer directly contacts the first vertical expansion inducing layer when the first bonding structure is hybrid-bonded to the second bonding structure (Figs. 6-7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 10, 12-13, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park.
Regarding claim 3, while Park teaches a thickness for the first vertical expansion including layer (130) (paragraph 24), Park does not explicitly teach thicknesses for the second vertical expansion inducing layer (110) and silicon oxide layer (120) to determine the thickness comparisons among the first vertical expansion including layer, the second vertical expansion including layers, and the silicon oxide layer as claimed. Nevertheless, it would have been obvious to one of ordinary skill in the art to adjust the thicknesses/volumes of the layers listed above (110, 120, and 130 from Park) by a routine experimentation in order to obtain the optimal thickness ranges for the layers and to obtain the desired comparisons between or among layers as claimed. It has held that discovering an optimum or workable ranges involves only routine skill in the art. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation. In re Aller, 105 USPQ 233. Furthermore, if the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not performed different than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
Regarding claims 10, 12-13, 16, and 19, the reason for rejecting claim 3 as discussed above is similarly applied for rejecting claim 10 reciting “a thickness of the upper region of the bonding insulation layer is greater than a thickness of the middle region of the bonding insulation layer”, claim 12 reciting “a volume ratio of the first dielectric layer is greater than a volume ratio of the second dielectric layer”, claim 13 reciting “a thickness of the first dielectric layer is about 40% to about 90% of a total thickness of the bonding insulation layer”, claim 16 reciting “the first upper vertical expansion including layer is formed having a first thickness corresponding to about 40% to about 90% of a thickness of the first bonding insulation layer”, and claim 19 reciting “the second upper vertical expansion including layer is formed having a thickness corresponding to about 40% to about 90% of a thickness of the second bonding insulation layer”.
Claims 5, 9, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1, 6, 11, and 15 above, and further in view of Liu et al. (US 2016/0358882 A1; hereinafter “Liu”).
Regarding claims 5, 9, 14, and 18, Park does not explicitly teach that the first insulating interlayer 110 (the second vertical expansion including layer for claim 5, the third dielectric material for claims 9 and 14, the first lower vertical expansion inducing layer for claim 18) and the second insulating interlayer 210 (the second lower vertical expansion including layer for claim 18) comprise at least one of silicon nitride material and silicon carbon nitride material. However, Park does not limit the material choice for the first insulating interlayer 110 and the second insulating interlayer 210 (paragraph 22 and 34-35) and Liu teaches a hybrid bonding structure (Fig. 5 and paragraphs 29-30), comprising: a second passivation layer 113 for a first wafer 100 and a second passivation layer 113 for a second wafer 500, equivalent to Park’s first and second insulating interlayers 110 and 210, wherein the second passivation layer 113 is formed of SiN (Fig. 5 and paragraphs 18 and 29). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Park with that of Liu in order to utilize readily available insulating material such as SiN for forming the predictable bonding insulation layer for the bonding structure.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL WHALEN/Primary Examiner, Art Unit 2893