Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the Terminal Disclaimer filed 05/15/2026 and the amendment filed 03/04/2026.
Claims 1-9, 10-17, 18-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9, 10-17, 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2-9, 10, 11-17, 18, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cowperthwaite et al. ( US 20230297421, hereinafter, Cowperthwaite’s 421) in view of Lee et al. ( US 20190286991, hereinafter, Lee’s 991).
Regarding to the claim 1, US 20230297421 teaches a system on a chip (SoC) [see Figure 13, item 1300, paragraph 0233] , comprising:
At least one central processing unit (CPU) [see Paragraphs 0226 & 0260 & 0261]
An artificial intelligent (machine learning ML) [see Paragraphs 0180-0184] accelerator, comprising:
An array of data processing engines ( compute engine TILE 1640A, 1640B, 1640C, 1640D) [see Figure 16C];
A network on chip (NoC) [see Figure 36A and Paragraph 0451 ];
An Input-Output Memory Management Unit ( IOMMU) comprising circuitry configured to perform a virtual to physical translation [see Figure 3C and Paragraphs 0103 & 0104 ]; wherein the IOMMU is coupled to the DPEs via the NoC [see Paragraph 0278 ] ( there is a fabric that connects the IOMMU 364 with DPEs 370).
However, US 20230297421 does not explicitly teach an interface communicatively coupling the CPU to the IOMMU in the AI accelerator.
US 20190286991, from the same or similar fields of endeavor, teaches an interface communicatively coupling the CPU (GPU 120) to the IOMMU 130 in the AI (Machine Learning operations) accelerator [see Figure 1 and Paragraph 0034].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of US 20230297421 in view of US 20190286991 because US 20190286991 suggests that there is a need for an efficient memory management scheme to enable in-storage machine learning training.
Regarding to the claim 2, US 20230297421 further teaches wherein the IOMMU 364 is configured to translate virtual addresses used by the Al accelerator to physical addresses used to store data in memory before transmitting the data from the Al accelerator to the interface (wherein the IOMMU 364 is configured to translate virtual addresses used by the Al accelerator to physical addresses used to store data in memory before transmitting the data from the Al accelerator to the interface
) [see Figure 3C and Figure 13 and Paragraphs 0103 – 0104 ].
Regarding to the claim 3, US 20230297421 further teaches wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the array of DPEs, through the NoC, and to the IOMMU ( wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the array of DPEs, through the NoC, and to the IOMMU) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 4, US 20230297421 further teaches wherein the memory mapped virtual addresses are Advanced eXtensible Interface (AXI) memory-mapped (MM) virtual addresses (wherein the memory mapped virtual addresses are Advanced eXtensible Interface (AXI) memory-mapped (MM) virtual addresses [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 5, US 20230297421 further teaches wherein the interface is a second NoC, wherein the second NoC is larger than the NoC in the Al accelerator (wherein the interface is a second NoC, wherein the second NoC is larger than the NoC in the Al accelerator) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 6, US 20230297421 further teaches a graphics processing unit (GPU), wherein the interface communicatively couples the GPU to the CPU ( a graphics processing unit (GPU), wherein the interface communicatively couples the GPU to the CPU ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 7, US 20230297421 further teaches at least one memory controller, wherein the interface communicatively couples the memory controller to the CPU and to the Al accelerator ( at least one memory controller, wherein the interface communicatively couples the memory controller to the CPU and to the Al accelerator
) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 8, US 20230297421 further teaches wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other ( wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 9, US 20230297421 further teaches wherein the CPU is configured to transmit instructions, via the interface, to the Al accelerator to perform Al tasks ( wherein the CPU is configured to transmit instructions, via the interface, to the Al accelerator to perform Al tasks ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 10, US 20230297421 teaches a method, comprising:
Receiving an instruction at an artificial intelligent (AI) (Machine Learning (ML)) accelerator to perform an AI task from a central processing unit (CPUs 361 ), wherein the CPU and the AI (Machine Learning (ML)) accelerator are disposed on a same integrated circuit (IC)) [see Figure 3C];
Performing the AI (Machine Learning) task using data processing engines (GFX CORES 370) in the AI (Machine Learning ) accelerator [see Figure 3C]
Transmitting data generated by the DPEs ( GFX CORES 370) when performing the AI task to network on chip (NoC) [see Paragraph 0278 ] in the AI (Machine Learning ) accelerator;
Performing, at an Input-Output Memory Management Unit (IOMMU 364) an address translation [see Figure 3C and Paragraphs 0103 – 104] on the data received from the NoC [see Paragraph 0278] ;
Transmitting the address translated data to the CPU 361 or a memory controller 367 in the IC.
However, US 20230297421 does not explicitly teach an IOMMU in the AI accelerator.
US 20190286991, from the same or similar fields of endeavor, teaches performing, at an IOMMU in the AI (Machine Learning ML) accelerator, an address translation on the data received from the NoC [see Paragraph 0034 ].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of US 20230297421 in view of US 20190286991 because US 20190286991 suggests that there is a need for an efficient memory management scheme to enable in-storage machine learning training.
Regarding to the claim 11, US 20230297421 teaches performing the address translation comprises: translating virtual addresses used by the Al accelerator to physical addresses used to store the address translated data in at least one of caches in the CPU or in an external memory (performing the address translation comprises: translating virtual addresses used by the Al accelerator to physical addresses used to store the address translated data in at least one of caches in the CPU or in an external memory ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 12, US 20230297421 further teaches wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the DPEs, through the NoC, and to the IOMMU ( wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the DPEs, through the NoC, and to the IOMMU ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 13, US 20230297421 further teaches wherein the memory mapped virtual addresses are AXI MM virtual addresses (wherein the memory mapped virtual addresses are AXI MM virtual addresses) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 14, US 20230297421 further teaches wherein transmitting the address translated data to the CPU or the memory controller is performed using an interface in the IC, wherein the interface is a second NoC that is larger than the NoC in the Al accelerator ( wherein transmitting the address translated data to the CPU or the memory controller is performed using an interface in the IC, wherein the interface is a second NoC that is larger than the NoC in the Al accelerator ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 15, US 20230297421 further teaches wherein the IC comprises a GPU, wherein the interface communicatively couples the GPU to the CPU (wherein the IC comprises a GPU, wherein the interface communicatively couples the GPU to the CPU) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 16, US 20230297421 further teaches wherein the interface communicatively couples the memory controller to the CPU and to the Al accelerator ( wherein the interface communicatively couples the memory controller to the CPU and to the Al accelerator ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 17, US 20230297421 further teaches wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs transmit data between each other when performing the Al task ( wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs transmit data between each other when performing the Al task ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 18, US 20230297421 teaches a system, comprising:
An integrated circuit (IC), comprising:
At least one central processing unit (CPU) [see Paragraphs 0226 & 0260 & 0261]
An AI accelerator (Machine Learning ML) [see Paragraphs 0180-0184] , comprising
An array of data processing engines ( compute engine TILE 1640A, 1640B, 1640C, 1640D) [see Figure 16C];
A network on chip (NoC) [see Figure 36A and Paragraph 0451 ];
Address translation circuitry (IOMMU 364 ) [see Figure 3C ] configured to perform a virtual to physical address translation [see Figure 3C and Paragraphs 0103 – 0104], wherein the address translation (IOMMU 364) is coupled to the DPEs (Cores 370) via the NoC (network on-chip ) [see Paragraph 0278],
A memory controller 367 [see Figure 3C], and
An interface communicatively coupling the CPU 361 to the address translation circuitry 364 in the AI (Machine Learning (ML)) accelerator and the memory controller 367; and
At least one external memory 366 coupled to the memory controller 367 in the IC [see Figure 3C].
However, US 20230297421 does not explicitly teach an AI accelerator, comprising.. address translation.
US 20190286991, from the same or similar fields of endeavor, teaches an AI (Machine Learning ML) accelerator, comprising an address translation (IOMMU 364) [see Figure 1 and Paragraph 0034].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of US 20230297421 in view of US 20190286991 because US 20190286991 suggests that there is a need for an efficient memory management scheme to enable in-storage machine learning training.
Regarding to the claim 19, US 20230297421 further teaches wherein the address translation circuitry is configured to translate virtual address used by the Al accelerator to physical addresses used to store data in the external memory before transmitting the data from the Al accelerator to the interface ( wherein the address translation circuitry is configured to translate virtual address used by the Al accelerator to physical addresses used to store data in the external memory before transmitting the data from the Al accelerator to the interface ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Regarding to the claim 20, US 20230297421 further teaches wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the DPEs, through the NoC, and to the address translation circuitry ( wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the DPEs, through the NoC, and to the address translation circuitry ) [ see Figure 3C and Figure 13 and Paragraphs 0103 - -0104 and 0278 ].
Conclusion
Claim(s) 1, 2, 6, 7, 8, 9, 10, 11, 17, 18, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. ( US 20240135007, hereinafter, Zeng’s 007 ) in view of KANDULA et al. ( US 20240219462, hereinafter, KANDULA’s 462 ), and further in view of PANDE et al. ( US 20240411718 , hereinafter, PANDE’s 718 ).
Regarding to the claim 1, US 20240135007 teaches A system on a chip (SoC) (SOC 30 ) [see Figure 1 and Paragraph 0015] , comprising:
at least one central processing unit (CPU) (a central processing unit (CPU) 300 ;
an artificial intelligence (AI) accelerator (the AI/ML accelerator 320 ) , comprising: an array of data processing engines ( array of Accelerators 322 ), and
an Input-Output Memory Management Unit (IOMMU 340 );
an interface communicatively coupling the CPU 300 to the IOMMU 340 in the AL accelerator 320 [see the Figure 3 and Paragraphs 0018 - 0024 ]
( [0018] FIG. 3 shows a system on chip (SOC) 30 with a DRAM 360 according to an embodiment of the present disclosure. The SOC 30 may comprise a secure processing unit (SPU) 310, an artificial intelligence/machine learning accelerator (AI/ML accelerator) 320, a inline cypher engine 330, an input-output memory management unit (IOMMU) 340, a micro processing unit (MPU) 350, a multimedia system memory 370 and a central processing unit (CPU) 300. The secure processing unit (SPU) 310 is configured to store information such as biometrics of users. The biometrics of the users may contain a face model description. The artificial intelligence/machine learning accelerator (AI/ML accelerator) 320 is configured to process images, and analyze the biometrics of the users. The AI/ML accelerator 320 comprises a micro control unit (MCU) 321 configured to intelligently link access identifications (IDs) to on-chip version numbers (VNs). The inline cypher engine 330 is coupled to the AI/ML accelerator 320 and the SPU 310, and configured to receive a register file from the MCU 321, encrypt data received from the AI/ML accelerator 320, and compare the biometrics of the users received from the SPU 310 with the data. The IOMMU 340 is coupled to the inline cypher engine 330 and configured to access the inline cypher engine 330. The MPU 350 is coupled to the IOMMU 340 and configured to control the DRAM 360 and control the IOMMU 340 to access the inline cypher engine 330. The CPU 300 is coupled to the SPU 310 and the AI/ML accelerator 320, and configured to control the SPU 310 and the AI/ML accelerator 320. The multimedia system memory 370 is coupled to the AI/ML accelerator 320 and configured to save the images and transmit the images to the AI/ML accelerator 320).
However, US 20240135007 does not explicitly teach the system on a chip (SoC), comprising a network on chip (NoC).
US 20240219462, from the same or similar fields of endeavor, teaches a system on a chip (SoC), comprising: at least one central processor unit (CPU); a network on chip (NoC) [see the Abstract ], and an Input-Ouput Memory Management Unit ( IOMMU) comprising circuitry configured to perform a virtual to physical address translation, wherein the IOMMU is coupled to the array DPEs (AI accelerators 322 ) ([0048] According to some examples, a first imitation flow can include transaction 5.1 originating from NoC UBA 120. Transaction 5.1, for example, includes an address translation service (ATS) request to VTU 132-2. For these examples, VTU 132-2 can function as a type of input/output memory management unit (IOMMU) to perform virtual to physical memory address translations for a direct memory access (DMA) of system memory. For these examples, transaction 5.2 originating from VTU 132-2 includes a successful ATS completion message that includes a translated address that was generated in response to the ATS request. NoC UBA 120 reads the ATS completion message to obtain the translated address and then uses attribute information associated with this first imitation flow (e.g., included in configuration registers 292) to continue the first imitation flow. The first imitation flow is continued via transaction 5.3 that is routed to memory controller 125 to complete the DMA of system memory using the translated address and to store data (e.g., obtained from the attribute information associated with the first imitation flow) [see Paragraph 0048],
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the system of US 20240135007 in view of US 20240219462 because US 20240219462 suggests that A next generation ML-accelerator system-on-chip (SoC) having an on-chip video decoder module to enable single chip video/imaging centric ML applications is desired.
However, US 20240135007 and US 20240219462 do not explicitly teach an artificial intelligence (AI) accelerator, comprising: a network on chip (NoC) .
US 20240411718, from the same or similar fields of endeavor, teaches a system on a chip (SoC) [see Figure 3] , comprising at least one central processor unit (CPU 360) , AI accelerator comprising array of DPEs (AI/ML accelerator core 310-1, 310-2, 310-3…310-N ) , a network on chip (NoC), and an input output memory management unit, wherein the input output memory management unit is coupled to the array of AI/ML accelerator cores via the NoC [see Figure 3 and Paragraphs 0043 & 0049 ].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the combined system (US 20240135007 and US 20240219462), and further in view of US 20240411718 because US 20240411718 suggests that off-chip encryption needs interface between a system on chip (SOC) and DRAM, thus off-chip encryption lacks of high security. In addition, the cost of off-chip encryption is higher than on-chip encryption. A secure and lower power solution is needed.
Note: [0028] The accelerator 120 includes an AI engine array 205 that includes a plurality of DPEs 210 ( which can also be referred to as AI engines)
Regarding to the claim 2, US 20240135007 further teaches wherein the IOMMU is configured to translate virtual addresses used by the AI accelerator to physical addresses used to store data in memory before transmitting the data from the AI accelerator to the interface ( wherein the IOMMU is configured to translate virtual addresses used by the AI accelerator to physical addresses used to store data in memory before transmitting the data from the AI accelerator to the interface ) [see the Figure 3 and Paragraphs 0018 - 0024 ].
Regarding to the claim 6, US 20240135007 further teaches a graphics processing unit (GPU), wherein the interface communicatively couples the GPU to the CPU (a graphics processing unit (GPU), wherein the interface communicatively couples the GPU to the CPU) [see the Figure 3 and Paragraphs 0018 - 0024 ].
Regarding to the claim 7, US 20240135007 further teaches at least one memory controller, wherein the interface communicatively couples the memory controller to the CPU and to the AI accelerator (at least one memory controller, wherein the interface communicatively couples the memory controller to the CPU and to the AI accelerator)
[see the Figure 3 and Paragraphs 0018 - 0024 ].
Regarding to the claim 8, US 20240135007 further teaches wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other (wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other) [see the Figure 3 and Paragraphs 0018 - 0024 ].
Regarding to the claim 9, US 20240135007 further teaches wherein the CPU is configured to transmit instructions, via the interface, to the AI accelerator to perform AI tasks (wherein the CPU is configured to transmit instructions, via the interface, to the AI accelerator to perform AI tasks ) [see the Figure 3 and Paragraphs 0018 - 0024 ].
Regarding to the claim 10, US 20240135007 teaches a method, comprising:
receiving an instruction at an AI accelerator (AI/ML Accelerator 320) to perform an AI task from a CPU (CPU 300 ) , wherein the CPU (CPUC 300) and the AI accelerator (AI/ML Accelerator 320) are disposed on a same integrated circuit (IC) (SoC 30) ;
performing the AI task using DPEs (Accelerators 322 in the AI/ML Accelerator 320 ) [see Figure 3] in the AI accelerator;
However, US 20240135007 does not explicitly teach performing, at an IOMMU in the AI accelerator, an address translation on the data received from the NoC; and transmitting the address translated data to the CPU or a memory controller in the IC.
US 20240219462, from the same or similar fields of endeavor, teaches performing, at an IOMMU in the AI accelerator, an address translation on the data received from the NoC; and transmitting the address translated data to the CPU or a memory controller in the IC (performing, at an IOMMU in the AI accelerator, an address translation on the data received from the NoC; and transmitting the address translated data to the CPU or a memory controller in the IC) [see Paragraph 0048 ].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the system of US 20240135007 in view of US 20240219462 because US 20240219462 suggests that A next generation ML-accelerator system-on-chip (SoC) having an on-chip video decoder module to enable single chip video/imaging centric ML applications is desired.
However, US 20240135007 and US 20240219462 do not explicitly teach transmitting data generated by the DPEs when performing the AI task to a NoC in the AI accelerator;
US 20240411718, from the same or similar fields of endeavor, teaches transmitting data generated by the DPEs when performing the AI task to a NoC in the AI accelerator (transmitting data generated by the DPEs when performing the AI task to a NoC in the AI accelerator ) [see Figure 3 and Paragraphs 0043 & 0049 ].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the combined system (US 20240135007 and US 20240219462), and further in view of US 20240411718 because US 20240411718 suggests that off-chip encryption needs interface between a system on chip (SOC) and DRAM, thus off-chip encryption lacks of high security. In addition, the cost of off-chip encryption is higher than on-chip encryption. A secure and lower power solution is needed.
Regarding to the claim 11, US 20240135007 further teaches performing the address translation comprises: translating virtual addresses used by the AI accelerator to physical addresses used to store the address translated data in at least one of caches in the CPU or in an external memory (performing the address translation comprises: translating virtual addresses used by the AI accelerator to physical addresses used to store the address translated data in at least one of caches in the CPU or in an external memory) [see the Figure 3 and Paragraphs 0018 - 0024 ].
Regarding to the claim 17, US 20240135007 further teaches wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs transmit data between each other when performing the AI task (wherein each of the DPEs comprises a core, a memory module, and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs transmit data between each other when performing the AI task) [see the Figure 3 and Paragraphs 0018 - 0024 ].
Regarding to the claim 18, US 20240135007 teaches a system, comprising:
An IC (SoC 30) [see Figure 3], comprising:
At least one CPU 300 [see Figure 3],
An AI accelerator 320, comprising
DPEs (Accelerators 322), and
address translation circuitry (IOMMU ),
a memory controller (a memory controller) [see Figure 3 ] ; and
at least one external memory coupled to the memory controller in the IC (at least one external memory coupled to the memory controller in the SoC 30 ) [see the Figure 3 and Paragraphs 0018 - 0024 ].
However, US 20240135007 does not explicitly teach address translation circuitry configured to perform a virtual to physical address translation, wherein the address translation circuitry is coupled to the DPEs.
US 20240219462, from the same or similar fields of endeavor, teaches address translation circuitry configured to perform a virtual to physical address translation, wherein the address translation circuitry is coupled to the DPEs (address translation circuitry configured to perform a virtual to physical address translation, wherein the address translation circuitry is coupled to the DPEs via the NoC) [see Paragraph 0048].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the system of US 20240135007 in view of US 20240219462 because US 20240219462 suggests that A next generation ML-accelerator system-on-chip (SoC) having an on-chip video decoder module to enable single chip video/imaging centric ML applications is desired.
However, US 20240135007 and US 20240219462 do not explicitly teach wherein the address translation circuitry is coupled to the DPEs via the NoC.
US 20240411718, from the same or similar fields of endeavor, teaches wherein the address translation circuitry is coupled to the DPEs via the NoC (wherein the address translation circuitry is coupled to the DPEs via the NoC) [see Figure 3 and Paragraphs 0043 & 0049 ].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the combined system (US 20240135007 and US 20240219462), and further in view of US 20240411718 because US 20240411718 suggests that off-chip encryption needs interface between a system on chip (SOC) and DRAM, thus off-chip encryption lacks of high security. In addition, the cost of off-chip encryption is higher than on-chip encryption. A secure and lower power solution is needed.
Regarding to the claim 19, US 20240135007 further teaches wherein the address translation circuitry is configured to translate virtual address used by the AI accelerator to physical addresses used to store data in the external memory before transmitting the data from the AI accelerator to the interface (wherein the address translation circuitry is configured to translate virtual address used by the AI accelerator to physical addresses used to store data in the external memory before transmitting the data from the AI accelerator to the interface) [see the Figure 3 and Paragraphs 0018 - 0024 ].
Allowable Subject Matter
Claims 3, 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim(s) 1, 3 and their respective dependents is/are allowed.
The prior art fails to disclose “ wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the array of DPEs, through the NoC, and to the IOMMU”.
Claims 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim(s) 1, 5 and their respective dependents is/are allowed.
The prior art fails to disclose “wherein the interface is a second NoC, wherein the second NoC is larger than the NoC in the AI accelerator ”.
Claims 12, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim(s) 10, 12 and their respective dependents is/are allowed.
The prior art fails to disclose “wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the DPEs, through the NoC, and to the IOMMU”.
Claims 14, 15, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim(s) 10, 14 and their respective dependents is/are allowed.
The prior art fails to disclose “wherein transmitting the address translated data to the CPU or the memory controller is performed using an interface in the IC, wherein the interface is a second NoC that is larger than the NoC in the AI accelerator”.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim(s) 18, 20 and their respective dependents is/are allowed.
The prior art fails to disclose “wherein the virtual addresses are memory mapped virtual addresses, wherein the memory mapped virtual addresses are used to transmit the data from the DPEs, through the NoC, and to the address translation circuitry ”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUONG T HO whose telephone number is (571)272-3133. The examiner can normally be reached 7:30-4:00.
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/CHUONG T HO/Examiner, Art Unit 2412
Prosecution Insights