Prosecution Insights
Last updated: October 02, 2026
Application No. 18/394,893

Performing Coalesced Storage Operations

Final Rejection §103
Filed
Dec 22, 2023
Priority
Nov 18, 2018 — provisional 62/768,952 +5 more
Examiner
MAMO, ELIAS
Art Unit
2184
Tech Center
2100 — Computer Architecture & Software
Assignee
Pure Storage Inc.
OA Round
6 (Final)
83%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
776 granted / 937 resolved
+27.8% vs TC avg
Moderate +6% lift
Without
With
+5.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
953
Total Applications
across all art units

Statute-Specific Performance

§101
7.1%
-32.9% vs TC avg
§103
60.5%
+20.5% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
12.7%
-27.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 937 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 21, 22, 24-29, 31-36, 38-41 are rejected under 35 U.S.C. 103 as being unpatentable over Wells et al. (US 2017/0344605), hereinafter referred to as Wells in view of Ravindranath et al. (US 9,785,360), hereinafter referred to as Ravindranath. Referring to claim 21, Wells teaches, as claimed, a method comprising: receiving two or more operations that are directed to non-adjacent memory regions in a cloud-based storage system (i.e.-receiving multiple write queries to write data across multiple cloud locations, page 2, ¶21, lines 10-13 and page 5, ¶48); and generating, by a storage system controller, from the two or more operations, a coalesced operation (i.e.-coalescing the multiple write queries, page 5, ¶50, lines 5-7), wherein the coalesced operation being a single command (page 2, ¶25, lines 8-11 and page 5, ¶50, lines 5-7); and performing the coalesced operation as a single command on a storage volume (see Abstract, lines 13-16; page 1, ¶4, lines 16-22; and page 2, ¶25, lines 8-9) of the cloud-based storage system (page 5, ¶45, lines 12-20; and ¶50, 4-7). However, Wells does not teach wherein the coalesced operation having an operational size below an operational size limit. On the other hand, Ravindranath disclsoes a method for generating a coalesced operation from two or more operations, wherein the coalesced operation having an operational size below an operational size limit (col. 7, lines 12-15, 23-25 and 38-43). Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Wells so that the coalesced operation having an operational size below an operational size limit and, the storage volume being of the cloud-based storage system, as taught Ravindranath. The motivation for doing so would have been to optimize read/write transactions from and/or to memory components; and saving network bandwidth directed toward distributed storage system. As to claim 22, the modified Wells teaches the method of claim 21, wherein generating the coalesced operation further comprises generating a coalesced write operation (see Wells, page 2, ¶25, lines 7-11). As to claim 24, the modified Wells innately teaches the method of claim 21, further comprising: performing the coalesced operation on two or more memory regions in the storage volume that are adjacent to each other (see Wells, page 10, ¶94, lines 13-16 and ¶105, lines 14-17). As to claim 25, the modified Wells in view of Ravindranath teaches the method of claim 21, wherein the storage volume is a block storage volume (see Ravindranath, col. 9, lines 32-33). As to claim 26, the modified Wells teaches the method of claim 25, wherein metadata for the block storage volume may be stored using an ordered log structured index (see Wells, page 2, ¶21, lines 5-8). As to claim 27, the modified Wells teaches the method of claim 21, wherein the two or more operations include a write operation (see Wells, page 2, ¶21, lines 11-13). Referring to claims 28, 29 and 31-34, the claims are substantially the same as claims 21, 22 and 24-27, hence the rejection of claims 21, 22 and 24-27 is applied accordingly. Referring to claims 35, 36 and 38-41, the claims are substantially the same as claims 21, 22, and 24-27, hence the rejection of claims 21, 22 and 24-27 is applied accordingly. Examiner’s note: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner. Response to Arguments Applicants’ arguments filed 06/17/2026 have been fully considered but they are not deemed to be persuasive. Applicants argued: Wells does not teach that the coalesced subquery corresponds to operations directed to non-adjacent memory regions. In fact, the Office Action fails to provide any reasoning as to how Wells teaches or suggests non-adjacent memory regions, as recited in independent claim 21. The Examiner disagrees with the above statement. Wells teaches method and system (i.e.-API services) that coordinates data across different cloud locations 1401, 1402, 1403, which are distant apart from one another (see fig. 1 and page 4, ¶44, lines 1-2). Furthermore, Wells teaches requesting data items that are stored in first, second, and third cloud location. The API services do cache the requested data items and generate a single optimized query to retrieve the requested data items (col 4., ¶44, lines 4-611-17). Applicants argued: Applicant submits that all claim language must be given patentable weight and that the pending rejection is incomplete as the rejection omits this language of the claims. …Should the rejection be maintained, finality of the Office Action is precluded as the rejection would constitute a new ground of rejection not facilitated by an amendment. The Examiner disagrees with the above statement. There are no new grounds of rejection, and the previous rejections are still maintained. NOTE: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner. Applicants argued: In particular, Ravindranath does not make any mention or teaching of non-adjacent memory regions. Rather, Ravindranath teaches systems and methods for optimizing input/output (I/O) operations to a storage device having mixed read and write operations by determining a current queue state for the read and write operations are taught. (Ravindranath, Abstract). The Examiner disagrees with the above statement. Ravindranath is not the cited reference as mentioning or teaching non-adjacent memory regions. Wells teaches method and system (i.e.-API services) which coordinates data across different cloud locations 1401, 1402, 1403, which are non-adjacent (see fig. 1 and page 4, ¶44, lines 1-2). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HENRY TSAI can be reached on 571-272-4176. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Elias Mamo/Primary Examiner, Art Unit 2184
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Prosecution Timeline

Show 16 earlier events
Dec 19, 2025
Applicant Interview (Telephonic)
Dec 27, 2025
Examiner Interview Summary
Jan 29, 2026
Request for Continued Examination
Feb 08, 2026
Response after Non-Final Action
Mar 18, 2026
Non-Final Rejection mailed — §103
Jun 09, 2026
Interview Requested
Jun 17, 2026
Response Filed
Aug 31, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
83%
Grant Probability
89%
With Interview (+5.9%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 937 resolved cases by this examiner. Grant probability derived from career allowance rate.

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