Prosecution Insights
Last updated: April 19, 2026
Application No. 18/395,038

Low Temperature Fabrication of Silicon Nitride Photonic Devices

Non-Final OA §102§103
Filed
Dec 22, 2023
Examiner
CAPUTO, LISA M
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
The Regents of the University of California
OA Round
1 (Non-Final)
8%
Grant Probability
At Risk
1-2
OA Rounds
2y 2m
To Grant
0%
With Interview

Examiner Intelligence

Grants only 8% of cases
8%
Career Allow Rate
3 granted / 38 resolved
-60.1% vs TC avg
Minimal -8% lift
Without
With
+-7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
22 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
25.4%
-14.6% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 38 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1-16, in the reply filed on 1/13/26 is acknowledged. Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/13/26. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-4, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin et al. (“Deuterated silicon dioxide for heterogeneous integration of ultra-low-loss waveguides”, from hereinafter “Jin”). Regarding claim 1, Jin teaches a method for fabricating an ultra-low loss waveguide (see page 3340) comprising: preparing a substrate including a lower cladding layer in a deposition chamber; flowing precursors comprising deuterated silane and nitrogen onto the lower cladding layer in the deposition chamber; subjecting the precursors to an inductively coupled plasma-plasma enhanced chemical vapor deposition (ICP-PECVD) process (see page 3341, left column, line 18) which disassociates the deuterated silane and nitrogen and deposits waveguide material of silicon nitride or silicon oxynitride onto the lower cladding layer; patterning the waveguide material into a patterned waveguide material; and depositing an upper cladding layer on the patterned waveguide material, wherein the ICP-PECVD process occurs at a temperature less than or equal to 250 °C (see abstract and conclusion). Regarding claims 3-4, Jin teaches the method of claim 1, wherein depositing the upper cladding layer comprises flowing vapor precursors of silane (see page 3340 lines 20-21), oxygen, and argon onto the lower patterned waveguide material and subjecting the vapor precursors to an ICP-PECVD process which disassociates the silane and oxygen and deposits waveguide material of silicon oxide onto the patterned waveguide material. The method of claim 1, further comprising depositing the lower cladding layer which comprises flowing vapor precursors of deuterated silane, oxygen onto the lower patterned waveguide material and subjecting the vapor precursors to an ICP-PECVD process which disassociates the silane and oxygen and deposits waveguide material of silicon oxide onto the substrate (see page 3340). Regarding claim 16, Jin teaches further comprising: flowing precursors comprising deuterated silane and nitrogen onto the upper cladding layer in the deposition chamber; subjecting the precursors to an ICP-PECVD process which disassociates the deuterated silane and nitrogen and deposits waveguide material of silicon nitride or silicon oxynitride onto the upper cladding layer; and patterning the waveguide material into a second patterned waveguide material (see pages 3340-3341). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 and 5-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Johnson et al. (USPGPUB 2003/0012538, from hereinafter “Johnson”). Regarding claim 2, Jin doesn’t specifically mention wherein the substrate comprises a substrate material selected from the group consisting of: silicon, quartz, a III-V semiconductor, and a polymer. Johnson, in the same field of endeavor, teaches the use of a notoriously well-known silicon substrate (see abstract and Figures 3A and 3B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a silicon substrate because it is well known in the art that silicon substrates are a good medium for optical devices and waveguides. Regarding claim 5, wherein the waveguide material has a thickness of less than 200 nm and regarding claim 9, wherein the waveguide material has a thickness of greater than or equal to 200 nm, Jin does not specifically teach a thickness of the waveguide material. Johnson teaches that in one embodiment of the present invention, deuterated gases (gases and vapors are used interchangeably herein), such as SiD.sub.4 and ND.sub.3 (D being deuterium), serving as precursors, along with a gaseous source of oxygen, such as nitrous-oxide (N.sub.2O) or oxygen (O.sub.2), are used for the chemical vapor deposition of silicon-oxynitride (SiO.sub.xN.sub.y:D) or other non-polymeric thin films on a cladding. The cladding is composed, for example, of silicon oxide (SiO.sub.2), phosphosilicate glass, fluorinated silicon oxide, or SiO.sub.xN.sub.y:D having an index of refraction less than that of the thin film. In an embodiment of the present invention, the cladding is formed on a substrate, such as silicon, quartz, glass, or other material containing germanium, fused silica, quartz, glass, sapphire, SiC, GaAs, InP, or silicon. In embodiments of the present invention, the thin film and the cladding formed on the substrate can vary in thickness and width, depending, for example, on the device being formed. In embodiments of the present invention, the cladding is formed with a thickness varying from 2 to 20 microns, and the thin film is formed with a thickness varying from about 0.5 to 5 microns. Other thicknesses of the cladding and the thin film are also usable in accordance with the present invention (see paragraph 13). The order of magnitude of the thin films in the micron range leads to one of ordinary skill in the art to know that it would be obvious to have a waveguide on the nm range. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the waveguide around the nm range for optimal operation with regards to the size of its components. Regarding claims 7, 11, and 14, Jin doesn’t specifically mention using a reactive ion etch process. Johnson teaches wherein etching the waveguide material is performed with a reactive ion etch process (see paragraph 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the reactive ion etch process because it is well known that the reactive ion etch process is an efficient way to produce semiconductor and optical waveguide items. Regarding claims 8, 12, and 15, Jin doesn’t specifically teach the use of ICP-RIE. Johnson teaches wherein the reactive ion etch process is an inductively coupled plasma-reactive ion etch (ICP-RIE) process, wherein the ICP-RIE process is performed at a temperature of 250 °C or less (see paragraph 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use ICP-RIE since it is well known in the art as an efficient way for ion etching semiconductor products. Jin further teaches regarding claim 6, wherein patterning the waveguide material comprises: coating the waveguide material with a photoresist; exposing the photoresist through a mask to transfer a pattern onto the photoresist; etching the waveguide material through the photoresist; and removing the photoresist. Additionally, regarding claim 10, The method of claim 9, wherein patterning the waveguide material comprises: depositing a hard mask layer on the waveguide material; coating the hard mask layer with a photoresist; exposing the photoresist through a mask to transfer a pattern onto the photoresist; etching the hard mask layer through the photoresist; removing the photoresist; etching the waveguide material through the hard mask layer; and removing the hard mask layer. Also, regarding claim 13, wherein depositing the hard mask layer comprises sputtering a hard mask material onto the waveguide material (see pages 3340-3341). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA M CAPUTO whose telephone number is (571)272-2388. The examiner can normally be reached Monday-Friday 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Dec 22, 2023
Application Filed
Apr 22, 2024
Response after Non-Final Action
Jan 24, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
8%
Grant Probability
0%
With Interview (-7.9%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 38 resolved cases by this examiner. Grant probability derived from career allow rate.

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