DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-3, 5-17 and 19-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
The claim limitation of “transforming” was not appeared or used to describe the action from “a plurality of vector instruction” to “a single fused micro-operation”. At most, the specification used the term “consolidating”. For example, the term “transform” has a meaning of “to change in composition or structure” while the term “consolidate” is understood as “to join together into one whole” (Merriam-Webster).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 8-10, 13-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Boyer (US 11,513,802).
Referring to claims 1, 15 and 20, Boyer discloses a method comprising:
detecting (fig. 5, check compressibility 502/504) a plurality of vector instructions (fig. 5, micro-operations 502) within a storage (fig. 4, UOP queue 212) of an integrated circuit (fig. 2, processor 200);
transforming (fig. 5, store pair of micro-operations in a single scheduled entry 506; fig. 4, scheduler compression logic 224) the plurality of vector instructions (fig. 4, UOP1, UOP2 212) into a single fused micro-operation (fig. 5, single scheduled entry 506; fig. 4, CUOP 1/2) based on the plurality of vector instructions satisfying a criterion (fig. 5, compressible 504; 4:48-52, compressibility rules),
wherein the satisfying the criteria comprises performing a logical operation (fig. 5, check compressibility rules 502; 4:52-64; 10:1-14) on a portion of an opcode (fig. 5, pairs of micro-operations in the queue 502; 5:5-27) included within each of the plurality of vector instructions;
loading (fig. 5, store in a single scheduler entry 506) the single fused micro-operation into a scheduler queue (fig. 4, scheduler 400; fig.2, scheduler 216/218/220; 15:41-49, scheduler queue) of the integrated circuit, and
executing the single fused micro-operation (fig. 4, execution unit404 executing CUOP 1/2; 8:31-34, micro-operations).
As to claims 2 and 16, Boyer discloses the method of claim 1, wherein executing the single fused micro-operation comprises:
receiving (fig. 4, picker logic 402 receives CUOP 1/2 from scheduler 400) the single vector instruction from the scheduler queue;
restoring (fig. 4, UOPEx1, UOPEx2 after picker logic 402) the plurality of vector instructions (fig. 7, first micro-operation 700, second micro-operation 704) from the single fused micro-operation (fig. 4, UOP1/UOP2 at 212 to CUOP1/2 at scheduler400, then restore as UOPEx1/UOPEx2 after picker logic 402); and
executing the plurality of vector instructions via an execution resource (fig. 4, execution unit 404; fig. 7, execution 704) of the integrated circuit.
As to claims 3 and 17, Boyer discloses the method of claim 2, wherein the execution resource comprises: a floating-point unit (7:56-65, floating point execution unit).
As to claims 5 and 19, Boyer discloses the criterion comprises
a certain opcode pair (fig. 5, a pair of micro-operation 502) identified in the plurality of vector instructions being eligible for consolidation (fig. 5, compressible 504); and
transforming the plurality of vector instructions into the single fused micro-operation comprises combining the plurality of vector instructions into the single fused micro-operation based on the certain opcode pair being eligible for combining (fig. 5, compressible 504 to Yes).
As to claim 8, Boyer discloses the method of claim 1, wherein:
the criterion comprises the plurality of vector instructions being positioned within a certain number of instructions (fig. 4, UOP1, UOP2, 212, i.e. one position away) from one another in the storage; and
consolidating the plurality of vector instructions into the single fused micro-operation comprises consolidating the plurality of vector instructions into the single fused micro-operation based on the plurality of vector instructions being positioned within the certain number of instructions from one another in the storage (fig. 4, compress into CUOP 1/2 in scheduler queue 400).
As to claim 9, Boyer discloses the method of claim 1, wherein the storage comprises a queue (fig. 5, queue 500).
As to claim 10, Boyer discloses the method of claim 1, wherein the single fused micro-operation complies with a constraint comprising: no more than one immediate value (fig. 3, IMM1 in portion 302) is included in the single fused micro-operation (8:53-58, an immediate value).
As to claim 13, Boyer discloses the method of claim 1, comprising:
receiving (fig. 4, picker logic 402 receive from scheduler 400) the single fused micro-operation from the scheduler queue; and
executing (fig. 4, execution unit 404) the single fused micro-operation via execution resource (fig. 2, processor 200) of the integrated circuit.
As to claim 14, Boyer discloses the method of claim 1, wherein the plurality of vector instructions comprises micro-operations (fig. 5, a pair of micro-operations 502) that is eligible for consolidation into a single micro-operation (fig. 5, single scheduler entry 502).
Allowable Subject Matter
After resolving issues under 35 USC 112(a), claims 6-7 and 11-12 will be viewed as objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The claim feature of consolidating based on the claim features of 1) a match between eligibility filter and bit string including in the opcode, 2) rendering output of first portion of an opcode with input in a lookup table indexed by second portion of the opcode, 3) satisfying of identified mask register as destination of first vector instruction, checking whether second vector satisfies consolidating criteria, and 4) refusing consolidate additional vector instruction as destination not being a mask register as required in dependent claims 6-7 and 11-12.
Response to Arguments
Applicant’s arguments have been fully considered, but they are not deemed to be persuasive.
Applicant argues that Boyer does not disclose “transforming the plurality of vector instructions into a single fused micro-instruction” (pp.9-10).
The scope of the claimed limitation is understood as applicant disclosed in fig. 6. For example, the claim is viewed as micro-operations 608 consolidated/transformed into a single/consolidated micro-operation. Boyer discloses UOP operations, such as UOP3, occupies a scheduler queue 400 entry for execution unit 404. Boyer discloses the first micro-operation UOP1 and second micro-operation UOP2 are compressed/fused into a single schedule queue 400 entry as CUOP 1/2 for execution unit 404. The compressed CUOP 1/2 is a single fused micro-instruction as it occupies single entry for execution unit 404 rather than two entries.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire in THREE MONTHS from the mailing date of this action. In the event a first reply is filled within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date of the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136 (a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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