DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9-13 and 18 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Moon et al. (US 11,726,721).
In reference to claim 1, Moon discloses in Figures 15-17 an integrated circuit die comprising: a set of electronic circuits (712a,b - 717a,b; Figure 16) disposed on a semiconductor material; at least one through-silicon via (TSV)(1101; Figure 17) that vertically spans the semiconductor material to transmit data signals; and a programmable delay element (718a,b; Figure 16) integrated with the set of electronic circuits on the semiconductor material and configured to delay data signals (WDQS1/WDQD2). The same applies to method claim 18.
In reference to claim 9, Moon discloses in Figure 15-17 a three-dimensional integrated circuit comprising: a base die (1110); a stack of at least two dies (1120-1150) electronically coupled to an interface (1111) of the base die (1110)(see Figure 17), wherein:
a programmable delay element (718a,b; Figure 16) is integrated with each die to control a timing of a data signal (WDQS1/WDQD2) (WDQS1/WDQD2); and
at least one through-silicon via (TSV)(1101; Figure 17) vertically spans each die to interconnect to other dies to transmit data signals.
In reference to claim 10 Moon discloses in Figure 17 wherein the at least two dies (1120-1150) are identically designed and vertically stacked by electronically coupling an interface of a first die (1120) with an interface of a second die (1130) such that at least one TSV (1101) of the first die (1120) is aligned to at least one TSV (1101) of the second die (1130).
In reference to claim 11 Moon discloses in Figure 17 wherein the stack of the at least two dies (1120-1150) is electronically coupled to the interface (1111) of the base die (1110) by electronically coupling the interface of the first die (1120) with the interface of the base die (1110) such that the at least one TSV (1101) of the first die (1120) is aligned to an electronic component of the base die (1110).
In reference to claim 12 Moon discloses in Figure 17 wherein the base die (1110) is configured to broadcast data to each die of the stack (1120-1150), wherein the base die (1110) broadcasts data to a distal die through at least one TSV (1101) of a proximal die.
In reference to claim 13 Moon discloses in Figure 17 wherein the base die (1110) is configured to receive data from each die of the stack (1120-1150), wherein the base die (1110) receives data from the distal die through the at least one TSV (1101) of the proximal die.
Allowable Subject Matter
Claims 2-8, 14-17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA F COX whose telephone number is (571)272-1741. The examiner can normally be reached M-F 7:00-4:30; off alt Fridays.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CASSANDRA F COX/Primary Examiner, Art Unit 2836
Prosecution Insights