Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/12/2025 has been entered.
Response to Arguments
Applicant's arguments with respect to claims 1, 8, and 15 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-8, 10-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Suryanarayanan et al. U.S. PGPUB No. 2015/0378412 in view of Hunt et al. U.S. PGPUB No. 2029/0190805.
Per Claim 1, Suryanarayanan discloses:
an apparatus (processor 110) comprising: an interface configured to receive workload information (Paragraph 28; Power management may be controlled by various hardware and may be triggered by workload.);
and circuitry (Paragraph 128; state control logic 1620) configured to cause the apparatus to operate at a power supply voltage of a plurality of power supply voltages (Paragraphs 119, 121, 128, and 129 discuss increasing operating voltage based on detected/predicted workload of memory instructions.)
wherein responsive to the workload information indicating a certain workload related to memory usage (Paragraphs 117; a memory subsystem may be monitored), the circuitry is configured to:
reduce an issue rate of memory requests to a memory subsystem (Paragraphs 125-128; “Upon detection of a memory instruction high power event, the reactive memory instruction tracking logic 1616 may signal to the memory OOO 1612 to throttle memory instructions for a determined period of time”.); and cause the apparatus to operate with a second power supply voltage that is lower than a current first power supply voltage (Paragraphs 119-130 teach a hybrid technique of utilizing instruction throttling and voltage guard band adjustment (reduction) to effectively reduce instances and severity of voltage droop based on detected/predicted memory instruction workloads. Paragraphs 161 and 162, Figure 19 numerals 1916, 1918, 1919, 1920, and 1924-1928 teach monitoring memory instructions, throttling said instructions and then changing a voltage guardband.).
Suryanarayanan teaches graphics workloads (Paragraph 79), which are known in the art to be memory latency sensitive, but does not specifically teach performing the voltage reduction and throttling steps based on the detected workload exhibiting sensitivity to memory-access latency based on memory-access performance characteristics.
However, Hunt teaches determining the memory bandwidth usage and memory latency of all system processes/workload (Paragraph 26, Fig. 3; numerals 301 and 302). Hunt further teaches determining whether a memory latency is at or below a contracted latency (Paragraph 27, Fig. 3; numeral 306; This reads on the claimed “exhibits sensitivity to memory-access latency based on memory-access performance characteristics” limitation since a measured memory latency is being used (performance characteristic) in the determination of whether a memory latency is above/below a certain level.). Hunt further teaches throttling both non-latency sensitive processes and latency sensitive (LS) processes based on at least the memory latency determination (Paragraphs 27 and 28, Fig. 3; numerals 306, 309, 310, 311, and 312).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform Suryanarayanan’s hybrid voltage droop prevention teachings by using Hunt’s memory latency sensitivity determination because it provides a method for optimizing system resource allocation to ensure memory-latency sensitive processes are guaranteed a minimum/floor bandwidth to ensure memory accesses are performed in a timely manner (Hunt; paragraph 11).
Per Claim 3, Suryanarayanan discloses the apparatus as recited in claim 1, wherein the circuitry is configured to cause the apparatus to operate with the second power supply voltage, subsequent to reducing the issue rate of memory requests to the memory subsystem (Paragraphs 121 and 128-130; The voltage guardband reduction represents a first voltage being reduced to a smaller voltage, and therefore teaches the first/second voltage guardband and power supply voltage relationship. Paragraphs 161 and 162, Figure 19 numerals 1916, 1918, 1919, 1920, and 1924-1928 teach monitoring memory instructions, throttling said instructions and then changing a voltage guardband.).
Per Claim 4, Hunt further teaches wherein the workload information further indicates the workload is not memory bandwidth sensitive (Paragraph 26, Fig. 3; Numerals 303[Wingdings font/0xE0]304 represent a workload that is not memory bandwidth sensitive since all latency sensitive processes are consuming their respective memory bandwidth use floors.).
Per Claim 5, Hunt further teaches wherein the workload information comprises an indication of a compute-intensive application (Paragraphs 21 and 26, Figure 3; Numeral 304 [Wingdings font/0xE0] 308 indicates a compute-intensive application since at least one latency sensitive process is consuming substantially above its memory bandwidth use floor.).
Per Claim 6, Suryanarayanan discloses the apparatus as recited in claim 1, wherein the first power supply voltage corresponds to a high-performance power-performance state (Paragraphs 26, 30, 66 disclose various performance and power states.).
Per Claim 7, Suryanarayanan discloses the apparatus as recited in claim 1, wherein the circuitry is further configured to issue memory requests based on the issue rate to a last-level cache of the memory subsystem shared by a plurality of clients (Paragraphs 33, 36, 49, and 164 teach last-level cache and Paragraphs 178, 186-203 disclose various examples of throttling the execution rate of memory instructions.).
Per Claims 8 and 10-14, please refer to the above rejection of claims 1 and 3-7 as the limitations are substantially similar and the mapping of limitations is equally applicable. Additionally, Suryanarayanan discloses the communication fabric (Circuitry and buses present within processor 110/1600 collectively considered “communication fabric” based on the definition provided in paragraph 14 of the Specification.).
Per Claim 15, Suryanarayanan discloses computing system comprising: a plurality of clients (Cores 120/1602, Fig. 1 and 16), each comprising circuitry configured to process tasks (Fig. 16); and a communication fabric comprising circuitry (Circuitry within processor 110/1600 collectively considered “communication fabric” based on the definition provided in paragraph 14 of the Specification.) to: receive workload information corresponding to tasks executed by circuitry of the plurality of clients (Paragraph 28; Power management may be controller by various hardware and may be triggered by workload.); generate, based on the workload information, an indication that a workload signifies a condition to trigger an action; and responsive to the indication: reduce an issue rate of memory requests to a memory subsystem to reduce memory bandwidth below a peak memory bandwidth (Paragraphs 125-128; “Upon detection of a memory instruction high power event, the reactive memory instruction tracking logic 1616 may signal to the memory OOO 1612 to throttle memory instructions for a determined period of time”.); and assign a second power supply voltage less than a current first power supply voltage to the communication fabric (Paragraphs 119-130 teach a hybrid technique of utilizing instruction throttling and voltage guard band adjustment (reduction) to effectively reduce instances and severity of voltage droop based on detected/predicted memory instruction workloads. Paragraphs 161 and 162, Figure 19 numerals 1916, 1918, 1919, 1920, and 1924-1928 teach monitoring memory instructions, throttling said instructions and then changing a voltage guardband.).
Suryanarayanan teaches graphics workloads (Paragraph 79), which are known in the art to be memory latency sensitive, but does not specifically teach performing the voltage reduction and throttling steps based on the detected workload exhibiting sensitivity to memory-access latency based on memory-access performance characteristics.
However, Hunt teaches determining the memory bandwidth usage and memory latency of all system processes/workload (Paragraph 26, Fig. 3; numerals 301 and 302). Hunt further teaches determining whether a memory latency is at or below a contracted latency (Paragraph 27, Fig. 3; numeral 306; This reads on the claimed “exhibits sensitivity to memory-access latency based on memory-access performance characteristics” limitation since a measured memory latency is being used (performance characteristic) in the determination of whether a memory latency is above/below a certain level.). Hunt further teaches throttling both non-latency sensitive processes and latency sensitive (LS) processes based on at least the memory latency determination (Paragraphs 27 and 28, Fig. 3; numerals 306, 309, 310, 311, and 312).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform Suryanarayanan’s hybrid voltage droop prevention teachings by using Hunt’s memory latency sensitivity determination because it provides a method for optimizing system resource allocation to ensure memory-latency sensitive processes are guaranteed a minimum/floor bandwidth to ensure memory accesses are performed in a timely manner (Hunt; paragraph 11).
Per Claims 17, 19, and 20, please refer to the above rejection of claims 3, 5, and 3 as the limitations are substantially similar and the mapping of limitations is equally applicable.
Per Claim 18, Suryanarayanan discloses the computing system as recited in claim 17, wherein the communication fabric is further configured to generate the indication, responsive to a rate of memory requests generated by the plurality of clients being less than a threshold (Paragraph 144).
Allowable Subject Matter
Claims 2, 9, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175