Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
Applicant's arguments with respect to claims 1, 8, and 15 have been considered but are moot in view of a new grounds of rejection with prior art references previously cited.
Claim Interpretation
Claims 1, 8, and 15 are amended to recite, “a memory latency sensitive workload”, as was originally claimed ON 12/23/2023.
As previously discussed in the Final Rejection on 9/11/2025, the Examiner contends that Khanna’s teaching of “compute-intensive application/workload” anticipates the “memory latency sensitive” classification that is applied to the workload in the claim. This mapping is supported by the broad interpretation applied to the workload being “memory latency sensitive”, as understood by one having ordinary skill in the art. When a limitation is broadly presented as such, the Examiner can refer to the Specification for further guidance on the intended scope for a guideline on interpreting the limitation. The Examiner highlights the following sections of the Applicant’s Specification which equates a workload from compute-intensive application as a “memory latency sensitive”:
“The Examiner highlights the following sections of the Applicant’s Specification which equates a workload from compute-intensive application as a “memory latency sensitive”:
Paragraph [13]: “For example, a compute-intensive application provides a memory latency sensitive workload.”
Paragraph [36]: “In an implementation, system management circuit 125 determines a type of workload based on the type of application providing the tasks. For example, a compute-intensive application provides a memory latency sensitive workload.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Khanna et al. U.S. PGPUB No. 2021/0116982 in view of Suryanarayanan et al. U.S. PGPUB No. 2015/0378412.
Per Claim 1, Khanna discloses:
an apparatus (computing system 102) comprising: an interface configured to receive workload information (Paragraphs 58-65, Telemetry data can include first/second compute utilization data; wherein the first/second compute utilization data may include workload data such as a type of instruction being executed by the CPU, the first acceleration resource, etc.);
and circuitry (Paragraph 68; Guard band controller 104 (numerals 104A-104F collectively considered to be guard band 104)) configured to cause the apparatus to operate at a power supply voltage of a plurality of power supply voltages (Paragraph 68; Guard band controller 104 (numerals 104A-104F collectively considered to be guard band 104) determines an adjustment to a guard band of a resource based on at least one of the classifications of the workload, the phase of the workload, or the determined guard band. NOTE: Selection and/or adjustments to a voltage guard band, as taught by Khanna, reads on the claimed causing the apparatus to operate at a power supply voltage, as the Applicant’s disclosure teaches this interpretation in at least Paragraphs 14, 38, and 46.);
wherein responsive to the workload information indicating that the workload is a memory latency sensitive workload (Paragraphs 62 and 63; “For example, the guard band controller 104A-F may determine that the computing system 102 is likely executing a first type of workload, which may correspond to a relatively high computationally-intensive application”; Paragraphs 113-116 teach a workload detector 340 for determining/classifying a workload into a plurality of classifications, including processor/memory/network bandwidth/cache memory/storage/accelerator intensive.),
the circuitry is configured to:
cause the apparatus to operate with a second power supply voltage that is lower than a current first power supply voltage (Paragraph 68 discusses adjusting the guard band based on at least the classification of a workload: “Advantageously, in some examples, the guard band controller 104A-F improves the performance of the computing system 102 by allocating power from a decrease in the guard band of a resource to an increase in an operating frequency of the resource based on at least one of the classification of the workload or the phase of the workload based on the telemetry data 122 or portion(s) thereof.” Paragraphs 138-141 discuss examples of reducing a guard band voltage to increase the ability of another system resource in response to the detection of a specific type of workload, which can be a computationally-intensive workload as previously discussed.).
Khanna further teaches instruction throttling circuit 210 that can effectuate instruction throttling to reduce the dynamic capacitance, which may reduce the dynamic power consumed by the processor core 204 (Paragraphs 76, 161, and 192). While Khanna teaches voltage adjustments based on detection of a memory specific workload, the throttling technique is not specific to the workload detection.
However, Suryanarayanan similarly teaches detecting a memory instruction high power event/workload and further teaches throttling memory instructions for a determined period of time to avoid voltage droop (Paragraphs 126).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate Suryanarayanan’s memory instruction throttling within the hybrid voltage adjustment and throttling teachings of Khanna because throttling instructions that cause a spike in power consumption can protect a processor during a voltage change/adjustment (Suryanarayanan; Paragraph 119).
Per Claim 2, Khanna discloses the apparatus as recited in claim 1, wherein the circuitry is further configured to redistribute at least a portion of a power budget allocated to the apparatus to one or more clients, responsive to the apparatus operating with the second power supply voltage (Paragraph 127; The processor core 204 may operate with increased performance by using the power previously consumed by the voltage guard band 230 to do an increased number of workloads. Paragraph 69 further identifies the processor core 204 as any CPU/processor/core within computing system 102, of which are responsible for running the applications 238 for processing the workloads.).
Per Claim 3, Khanna does not specifically teach the order of throttling memory instructions and then reducing a guard band voltage.
However, Suryanarayanan discloses this specific order of corrective actions based on a workload (Paragraphs 121 and 128-130; The voltage guardband reduction represents a first voltage being reduced to a smaller voltage, and therefore teaches the first/second voltage guardband and power supply voltage relationship. Paragraphs 161 and 162, Figure 19 numerals 1916, 1918, 1919, 1920, and 1924-1928 teach monitoring memory instructions, throttling said instructions and then changing a voltage guardband.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform the corrective actions of Khanna’s throttling and voltage reduction in the order as taught by Suryanarayanan because each corrective action (throttling vs. voltage reduction) has a different effect on the resources of the system and Suryanarayanan teaches that throttling instructions that cause a spike in power consumption can protect a processor during a voltage change/adjustment (Suryanarayanan; Paragraph 119).
Per Claim 4, Khanna discloses the apparatus as recited in claim 1, wherein the workload information further indicates the workload is not memory bandwidth sensitive (Paragraph 115; The workload classifier can assign a workload classification to a workload that is considered “intensive” according to a plurality of different system parameters. Identifying a workload as processor, network, or any of the other parameters not “memory” is considered the claimed “not memory bandwidth sensitive”.).
Per Claim 5, Khanna discloses the apparatus as recited in claim 1, wherein the workload information comprises an indication of a compute-intensive application (Paragraphs 62 and 115).
Per Claim 6, Khanna does not specifically mention the “power-performance states”, as claimed.
However, Suryanarayanan teaches wherein the first power supply voltage corresponds to a high-performance power-performance state (Paragraphs 26, 30, 66 disclose various performance and power states.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the high-computationally-intensive application/workload of Khanna to originally operate in a high-performance P-state, as taught by Suryanarayanan because high-performance resources are necessary to optimally perform computationally intensive workloads efficiently.
Per Claim 7, Khanna teaches cache utilization data associated with cache memory of a CPU (Paragraphs 61, 103), but does not specifically teach that memory requests are issued to a last-level cache of the memory subsystem shared by a plurality of clients.
However, Suryanarayanan discloses wherein the circuitry is further configured to issue memory requests based on the issue rate to a last-level cache of the memory subsystem shared by a plurality of clients (Paragraphs 33, 36, 49, and 164 teach last-level cache and Paragraphs 178, 186-203 disclose various examples of throttling the execution rate of memory instructions.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the memory requests/workload of Khanna to be of a last-level cache, as taught by Suryanarayanan, because Khanna teaches cache-centric workloads worth tracking via telemetry data.
Per Claims 8-14, please refer to the above rejection of claims 1-7 as the limitations are substantially similar and the mapping of limitations is equally applicable. Additionally, Khanna discloses the communication fabric (Bus 116 and the components connected thereto.).
Per Claim 15, Khanna discloses computing system comprising: a plurality of clients (Fig. 1; CPU 106, Acceleration resources A/B 108/110), each comprising circuitry configured to process tasks (Paragraphs 45 and 47); and a communication fabric comprising circuitry (Fig. 1, Bus 116 and the circuitry/components connected thereto comprise a “communication fabric”.) to:
receive workload information corresponding to tasks executed by circuitry of the plurality of clients; generate, based on the workload information, an indication that the workload is a memory latency sensitive workload (Paragraphs 58-65, Telemetry data can include first/second compute utilization data; wherein the first/second compute utilization data may include workload data such as a type of instruction being executed by the CPU, the first acceleration resource, etc. Paragraphs 62 and 63; “For example, the guard band controller 104A-F may determine that the computing system 102 is likely executing a first type of workload, which may correspond to a relatively high computationally-intensive application”);
and responsive to the indication: assign a second power supply voltage less than a current first power supply voltage to the communication fabric (Paragraph 68 discusses adjusting the guard band based on at least the classification of a workload: “Advantageously, in some examples, the guard band controller 104A-F improves the performance of the computing system 102 by allocating power from a decrease in the guard band of a resource to an increase in an operating frequency of the resource based on at least one of the classification of the workload or the phase of the workload based on the telemetry data 122 or portion(s) thereof.” Paragraphs 138-141 discuss examples of reducing a guard band voltage to increase the ability of another system resource in response to the detection of a specific type of workload, which can be a computationally-intensive workload as previously discussed.).
Khanna further teaches instruction throttling circuit 210 that can effectuate instruction throttling to reduce the dynamic capacitance, which may reduce the dynamic power consumed by the processor core 204 (Paragraphs 76, 161, and 192). While Khanna teaches voltage adjustments based on detection of a memory specific workload, the throttling technique is not specific to the workload detection.
However, Suryanarayanan similarly teaches detecting a memory instruction high power event/workload and further teaches throttling memory instructions for a determined period of time to avoid voltage droop (Paragraphs 126).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate Suryanarayanan’s memory instruction throttling within the hybrid voltage adjustment and throttling teachings of Khanna because throttling instructions that cause a spike in power consumption can protect a processor during a voltage change/adjustment (Suryanarayanan; Paragraph 119).
Per Claims 17, 19, and 20, please refer to the above rejection of claims 3, 5, and 3 as the limitations are substantially similar and the mapping of limitations is equally applicable.
Per Claim 18, Khanna does not specifically teach generating the indication, responsive to a rate of memory requests generated by the plurality of clients being less than a threshold.
However, Suryanarayanan teaches generating the indication, responsive to a rate of memory requests generated by the plurality of clients being less than a threshold (Paragraph 144).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for Khanna to trigger the indication responsive to a rate of memory requests generated being less than a threshold, as taught by Suryanarayanan, because it allows for a programmable threshold that can be tailored to a specific system and set of system characteristic (Suryanarayanan; Paragraph 144).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
Prosecution Insights