Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note: The Examiner note that the claims 1-5 are structure claims, thus “formed” is taken to be a product by process limitation and considered a non-limitation, in a product-by-process claim, it is the patentability of the claimed product and not of the recited steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by-process claim, a rejection based on sections 102 or 103 is fair. The Patent Office is not equipped to manufacture products by a myriad of processes put before it and then obtain prior art product and make physical comparisons therewith. In re Brown, 173 USPQ 685 (CCPA 1972). Also, a product-by-process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ I S at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product "gleaned" from the process steps, which must be determined in a "product by process" claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in "product by process" claims or not.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujihira et al. (US 20010035560 A1) hereafter referred to as Fujihira in view of Nishii et al. (US 20150021747 A1) hereafter referred to as Nishii
In regard to claim 1 Fujihira teaches a semiconductor device [see “FIG. 1 is a cross-sectional view of a pn junction diode 201 having a pn junction according to the first embodiment of the present invention” “FIG. 4(a) through FIG. 4(d) are cross-sectional views showing main process steps of a method for manufacturing the pn junction diode of the first embodiment”] comprising:
a semiconductor base [this includes both 2 and 1, see paragraph 0095 “n drift layer 2 is laminated by epitaxial growth on the n.sup.+ cathode layer 1 as a substrate, which is doped with arsenic, and has a resistivity of 0.004 .OMEGA..multidot.cm and a thickness of 350 .mu.m”] body;
an insulation layer [“oxide film 6”] formed on a surface of the semiconductor base body, the insulation layer having an opening [see Fig. 4(b) opening in “oxide film 6” for “anode electrode 5”] through which the surface of the semiconductor base body is exposed; and
a surface electrode [“anode electrode 5”] connected to the semiconductor base body at the opening, wherein
the semiconductor base body includes:
a drift region [“n drift layer 2 is laminated by epitaxial growth”] of a first conductive type;
a dopant region [“Subsequently, the oxide film 6 located inside the p ring region 12 is removed by photolithography, and the p.sup.- anode region 3a is formed by implantation of boron ions and thermal diffusion, as shown in FIG. 4(b). The acceleration voltage for ion implantation is 45 keV, and the dose amount is 1.times.10.sup.12 cm.sup.-2. After the ion implantation, annealing is conducted at 450.degree. C. for 30 min. The surface impurity concentration of the p.sup.- anode region 3a is 5.times.10.sup.15 cm.sup.-3, and the depth of junction between the p.sup.- anode region 3a and the n drift layer 2 is as small as about 0.3 .mu.m because the annealing temperature is low, and thermal diffusion hardly takes place”] of a second conductive type formed in a surface layer portion of the drift region; and
a peripheral dopant region [12 “the p ring region 12 and p peripheral region 8 are formed in a surface layer of the n drift layer 2, through implantation of boron ions and subsequent thermal diffusion, as shown in FIG. 4(a). The acceleration voltage for ion implantation is 45 keV, and the dose amount is 5.times.10.sup.13 cm.sup.2. After the ion implantation, annealing is conducted at 1150.degree. C. for 200 min. The surface impurity concentration of the p ring region 12 and p peripheral region 8 is about 2.times.10.sup.17 cm.sup.-3, and the diffusion depth is 3 .mu.m”] of the second conductive type formed [see above “formed” is taken to be a product by process limitation and considered a non-limitation] on a peripheral portion of the dopant region of the second conductive type in a surface layer portion of the drift region, having a region where the peripheral dopant region of the second conductive type overlaps [see that in Fig. 4(b) there is overlap, because even the region 12 is exposed by the opening in oxide film 6 during implantation of 3a, “the oxide film 6 located inside the p ring region 12 is removed by photolithography, and the p.sup.- anode region 3a is formed by implantation of boron ions and thermal diffusion, as shown in FIG. 4(b)”] with the dopant region of the second conductive type, the peripheral dopant region having dopant concentration higher [see that “surface impurity concentration of the p ring region 12 and p peripheral region 8 is about 2.times.10.sup.17 cm.sup.-3” whereas “surface impurity concentration of the p.sup.- anode region 3a is 5.times.10.sup.15 cm.sup.-3”] than dopant concentration of the dopant region of the second conductive type, wherein
the dopant region of the second conductive type has a high concentration region [see that in Fig. 4(b) there is overlap, because even the region 12 is exposed by the opening in oxide film 6 during implantation of 3a, thus in the overlap region the dopant is equal to that of 12 plus that of 3a] that is formed in a portion where the dopant region of the second conductive type overlaps with the peripheral dopant region and has higher dopant concentration [see the concentrations above] than other regions of the dopant region of the second conductive type,
a plurality of recombination centers [see “For lifetime control, gold or platinum is diffused at 700 to 800.degree. C” see “In the pn junction diodes of FIG. 37, 39, 40, lifetime killers for accelerating recombination of accumulated carriers are introduced by diffusion of Au or Pt, or irradiation of electron beams, so as to increase the switching speed”] are formed in the semiconductor base body,
an inner peripheral end of the peripheral dopant region [see Fig. 4(d) the inner side of “p ring region 12” is inside the opening in “oxide film 6”] on the surface of the semiconductor base body is positioned on an inner peripheral side of an end portion of the opening, and
that a length from the inner peripheral end of the peripheral dopant region to the end portion of the opening is [see Fig. 4(d)] greater than zero,
but does not actually state 0.01 µm or more to 30 µm or less.
However see the dimensions “the p ring region 12 and p peripheral region 8 are formed in a surface layer of the n drift layer 2, through implantation of boron ions and subsequent thermal diffusion, as shown in FIG. 4(a). The acceleration voltage for ion implantation is 45 keV, and the dose amount is 5.times.10.sup.13 cm.sup.2. After the ion implantation, annealing is conducted at 1150.degree. C. for 200 min. The surface impurity concentration of the p ring region 12 and p peripheral region 8 is about 2.times.10.sup.17 cm.sup.-3, and the diffusion depth is 3 .mu.m”, thus the distance from the lateral diffusion edge from the implant edge is not more than 3 .mu.m, see also an example dimension see paragraph 0180 “For example, a 3 mm-square diode”.
See Nishii Fig. 14, Fig. 15 see paragraph 0054-0059 “FIG. 14 is a cross-sectional view illustrating a diode according to Embodiment 2 of the present invention. The p-type anode layer 2 includes a first region 2a and a second region 2b which is provided around the periphery of the first region 2a, deeper than the first region 2a and has higher impurity concentration” “FIG. 15 is a diagram illustrating a relationship between a maximum interruptible current density and W2. W1 is 60 .mu.m. If W2 is greater than 60 .mu.m, it is evident that the maximum current density improves. Therefore, making W2 greater than W1 like the present embodiment improves the breakdown voltage”. See Fig. 15 shows that current density shown is flat when W2 greater than 60 i.e. (W2-W1) > 0 i.e. when the inner edge of 2b is within the opening in “oxide film 4”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “0.01 µm or more to 30 µm or less ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 3 Fujihira and Nishii as combined teaches wherein the high concentration region is formed in only [see that in Fig. 4(b) there is overlap, because even the region 12 is exposed by the opening in oxide film 6 during implantation of 3a, thus in the overlap region the dopant is equal to that of 12 plus that of 3a] a region where the dopant region of the second conductive type and the peripheral dopant region overlap with each other.
In regard to claim 4 Fujihira and Nishii as combined teaches wherein the dopant region of the second conductive type extends to [see that in Fig. 4(b) see “the oxide film 6 located inside the p ring region 12 is removed by photolithography, and the p.sup.- anode region 3a is formed by implantation of boron ions and thermal diffusion, as shown in FIG. 4(b)”, thus the implantation is upto the outer peripheral edge of the opening, and then diffusion causes more spreading ] an outer peripheral side of the opening.
[The Examiner notes that the broadest reasonable interpretation of "Within a range" means a value, item, or measurement falls between a specified minimum and maximum limit, inclusive of those boundaries]
In regard to claim 5 Fujihira and Nishii as combined does not specifically teach in Fig. 4 wherein the dopant concentration of the drift region falls within a range of from 1.0x10¹³ cm⁻³ to 1.0x10¹⁵ cm⁻³.
However see Fujihira paragraph 0004 “The n drift layer 2 is laminated by epitaxial growth on the n.sup.+ cathode layer 1 as a substrate. For example, the impurity concentrations of the n.sup.+ cathode layer 1 and n drift layer 2 are 1.times.10.sup.19 cm.sup.-3, and 1.times.10.sup.15 cm.sup.-3, respectively”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the dopant concentration of the drift region falls within a range of from 1.0x10¹³ cm⁻³ to 1.0x10¹⁵ cm⁻³ ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi et al. (US 20060278925 A1) hereafter referred to as Yamaguchi in view of Fujihira et al. (US 20010035560 A1) hereafter referred to as Fujihira
In regard to claim 2 Yamaguchi teaches a semiconductor device [ see Fig. 5C, see paragraph 0056 “FIGS. 4 and 5 are processing cross-sectional views each illustrating an example of a manufacturing process for the diode in FIG. 1”] comprising:
a semiconductor base [includes 1, 2, 3, 5 “In the first place, an n.sup.- type high-resistance substrate is prepared that is to be used as a material for the n.sup.- type base layer 1” “Next, by making impurities diffuse within the n.sup.- type high-resistance substrate, the n.sup.+ cathode layer 3 is formed” “Alternatively, a substrate having an n.sup.+ epitaxial layer on the surface of an n.sup.- type substrate may be provided in advance” “Thereafter, on the surface of the n.sup.- type base layer 1, the middle-concentration n type base layer 5 is formed through ion implantation and diffusion processing, or epitaxial growth”] body;
an insulation layer [“an insulating film 9 is formed on the surface of the junction termination region, through thermal oxidation or film growth”] formed on a surface of the semiconductor base body, the insulation layer having an opening [see Fig. 5C the opening in 9 where “anode electrode 8” can be seen] through which the surface of the semiconductor base body is exposed; and
a surface electrode connected to [see Fig. 5C the opening in 9 where “anode electrode 8” can be seen] the semiconductor base body at the opening, wherein
the semiconductor base body includes:
a drift region [includes at least “middle-concentration n type base layer 5”] of a first conductive type;
a dopant region [“p type anode layer 6”] of a second conductive type formed in a surface layer portion of the drift region; and
a peripheral dopant region [see p+ “junction termination layer 7”] of the second conductive type formed [see above “formed” is taken to be a product by process limitation and considered a non-limitation] on a peripheral portion [ see Fig. 5C] of the dopant region of the second conductive type in a surface layer portion of the drift region, having a region where the peripheral dopant region of the second conductive type overlaps [ see Fig. 5C] with the dopant region of the second conductive type, the peripheral dopant region having dopant concentration higher [see Fig. 5C see 7 is p+ whereas 6 is p) than dopant concentration of the dopant region of the second conductive type, wherein
the dopant region of the second conductive type has a high concentration region that is formed in a portion where [ see Fig. 5C, see that in the overlap region of 7 and 6 the concentration will that of 7 plus that of 6] the dopant region of the second conductive type overlaps with the peripheral dopant region and has higher dopant concentration than other regions [see Fig. 5C the rest of 6 has only the p concentration of 6] of the dopant region of the second conductive type,
a plurality of recombination centers [“the local lifetime control region 2 is formed in the low-concentration n.sup.- type base layer 1” “Next, after a charged particle beam of proton, helium, or the like is irradiated onto the cathode electrode 4 or the anode electrode 8, annealing processing is applied to the device to form the local lifetime control region 2 (FIG. 5C) in the n.sup.- type base layer 1”] are formed in the semiconductor base body,
an inner peripheral end of the peripheral dopant region on the surface of the semiconductor base body is located [see Fig. 5C see that the inner end of 7 is outside the opening in “insulating film 9” i.e. 7 is entirely underneath 9] at a same position as an end portion of the opening or on an outer peripheral side of the end portion of the opening, and
but does not specifically teach the dopant concentration of the high dopant region falls within a range of from 1.0x10¹⁶ cm⁻³ to 1.0x10²⁰ cm⁻³.
See Fujihira teaches “FIG. 1 is a cross-sectional view of a pn junction diode 201 having a pn junction according to the first embodiment of the present invention” “FIG. 4(a) through FIG. 4(d) are cross-sectional views showing main process steps of a method for manufacturing the pn junction diode of the first embodiment” “Subsequently, the oxide film 6 located inside the p ring region 12 is removed by photolithography, and the p.sup.- anode region 3a is formed by implantation of boron ions and thermal diffusion, as shown in FIG. 4(b). The acceleration voltage for ion implantation is 45 keV, and the dose amount is 1.times.10.sup.12 cm.sup.-2. After the ion implantation, annealing is conducted at 450.degree. C. for 30 min. The surface impurity concentration of the p.sup.- anode region 3a is 5.times.10.sup.15 cm.sup.-3, and the depth of junction between the p.sup.- anode region 3a and the n drift layer 2 is as small as about 0.3 .mu.m because the annealing temperature is low, and thermal diffusion hardly takes place” “the p ring region 12 and p peripheral region 8 are formed in a surface layer of the n drift layer 2, through implantation of boron ions and subsequent thermal diffusion, as shown in FIG. 4(a). The acceleration voltage for ion implantation is 45 keV, and the dose amount is 5.times.10.sup.13 cm.sup.2. After the ion implantation, annealing is conducted at 1150.degree. C. for 200 min. The surface impurity concentration of the p ring region 12 and p peripheral region 8 is about 2.times.10.sup.17 cm.sup.-3, and the diffusion depth is 3 .mu.m”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “the dopant concentration of the high dopant region falls within a range of from 1.0x10¹⁶ cm⁻³ to 1.0x10²⁰ cm⁻³ ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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