DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on December 26, 2023 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner suggests the following title “SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND EMITTER REGIONS IN CONTACT WITH TRENCH SIDEWALLS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE”.
Claim Objections
Claim 13, and 16-17 are objected to because of the following informalities:
claim 13, line 08,
“the contact region is provide from an end portion”
should recite
--the contact region is provided from an end portion--.
Claim 16, line 02,
“formed by an ion implantation using”
should recite
-- formed by ion implantation using --.
Claim 17, line 02,
“by an implantation to invert”
should recite
-- by ion implantation to invert --.
Claim 14 is objected to because of its dependency on claim 13. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9, 11-12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Naito et al. (US 2018/0366548 A1; hereinafter referred to as Naito).
Regarding claim 1. Naito discloses A semiconductor device (fig 1B, also zoomed view fig. 4) comprising:
a plurality of trench portions (30 and 40) provided on a front surface of a semiconductor substrate (10) and including a gate trench portion (40);
a drift region (18) of a first conductivity type (N-) provided in the semiconductor substrate (10);
a base region (14) of a second conductivity type (P-) provided above the drift region (18);
an emitter region (source 12) of the first conductivity type (N+) provided above (12 above 14) the base region (14) and having a doping concentration higher (12 has N+, 18 has N-) than that of the drift region (18); and
a contact region (28) of the second conductivity type (P+) provided above the base region (14) and having a doping concentration higher (28 has P+, 14 has P-) than that of the base region (14),
wherein the emitter region (source 12) is provided to be in contact (source 12 contacting 40) with a side wall of the gate trench portion (40) and terminates without extending (see left-side annotated fig 1B below) to a first trench portion (30) opposing to the gate trench portion (40) from among the plurality of trench portions (30 and 40) in a trench array direction (x-direction), and
wherein the contact region (28) is provided from an end portion of the emitter region (source 12) to a side wall (see right-side annotated fig1B below) of the first trench portion (30) in the trench array direction (x-direction).
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Regarding claim 2, Naito discloses the semiconductor device according to claim 1. Naito further discloses
wherein in a top view (x-y plane in annotated fig. 1A below) of the semiconductor substrate (10, shown above in claim 1), the emitter region (source 12) is discretely provided in a trench (30) extending direction (x-direction, see dashed lines annotated in fig. 1A below).
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Regarding claim 9, Naito discloses the semiconductor device according to claim 1. Naito further discloses
wherein a doping concentration of the contact region (28) is equal to or greater than 1E19 cm-3 and equal to or smaller than 2E20 cm-3 (“the first peak P1 of the contact layer 28 is approximately 1E20 cm-3” [0086, ln 02-03], “peaks of the doping concentration of the contact layer 28” [0087, ln 05-06], examiner interprets that 1E20 cm-3 addresses claimed range).
Regarding claim 15. Naito discloses a manufacturing method of a semiconductor device (fig 1B, also zoomed view fig. 4) comprising:
forming a plurality of trench portions (30 and 40) including a gate trench portion (40) on a front surface of a semiconductor substrate (10);
forming a drift region (18) of a first conductivity type (N-) in the semiconductor substrate (10);
forming a base region (14) of a second conductivity type (P-) above the drift region (18);
forming an emitter region (source 12) of the first conductivity type (N+) above (12 above 14) the base region (14), the emitter region (source 12) having a doping concentration higher (12 has N+, 18 has N-) than that of the drift region (18); and
forming a contact region (28) of the second conductivity type (P+) above the base region (14), the contact region (28) having a doping concentration higher (28 has P+, 14 has P-) than that of the base region (14),
wherein the emitter region (source 12) is formed to be in contact (source 12 contacting 40) with a side wall of the gate trench portion (40) and terminates without extending (see left-side annotated fig 1B below) to a first trench portion (30) opposing to the gate trench portion (40) in a trench array direction (x-direction), and
the contact region (28) is formed from an end portion of the emitter region (source 12) to a side wall (see right-side annotated fig1B below) of the first trench portion (30) in the trench array direction (x-direction).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Naito et al. (US 2018/0366548 A1; hereinafter referred to as Naito) in view of Imagawa et al. (US 2020/0287005 A1; hereinafter referred toas Imagawa).
Regarding claim 3. Naito discloses the semiconductor device according to claim 1. Naito does not disclose
wherein on the side wall of the gate trench portion, a length of the emitter region in the trench extending direction is greater than a length of the contact region in the trench extending direction.
Imagawa discloses an IGBT semiconductor device, and is therefore analogous art, specifically Imagawa teaches (fig 1, [0058])
wherein on the side wall of the gate trench portion (40), a length of the emitter region (12) in the trench extending direction (“extension direction between adjacent two of the trench portions” [0010] ln 12) is greater than a length of the contact region in the trench extending direction (“the emitter region in the cell may have a length, in the extension direction, which is greater than a length of the contact region” [0010] ln 16-18).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize an emitter region and contact region as disclosed by Naito and to include an emitter region that is greater in length than the contact region as taught by Imagawa because a large emitter region, which is the most heavily doped area of the transistor, allows the emitter region to inject a large density of conduction-band electrons toward the forward-biased junction of the transistor.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Naito et al. (US 2018/0366548 A1; hereinafter referred to as Naito) in view of Naito et al. (US 2016/0336435 A1; hereinafter referred to as Naito_435).
Regarding claim 4, Naito discloses the semiconductor device according to claim 1. Naito does not disclose
wherein a length of the emitter region in the trench array direction is equal to or greater than 0.1 μm and equal to or smaller than 1.0 μm.
Naito_435 teaches a SiC IGBT and is therefore analogous art, specifically Naito teaches ([0031], also fig 1)
wherein a length of the emitter region (42) in the trench array direction (fig 1) is equal to or greater than 0.1 μm and equal to or smaller than 1.0 μm (“the emitter region 42 in the first direction is 1 μm” [0031] ln 04, examiner interprets 1 μm to satisfy both ranges in limitation).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize an emitter region as disclosed by Naito and to include an emitter region in the micron range as disclosed by Naito_435 because emitter regions in the micron range are utilized in power devices such as IGBTs, to reduce on-state voltage, improve switching efficiency, and manage carrier concentration for faster performance. These micron-scale emitter dimensions allow for higher injection efficiency, which minimizes power losses in high-voltage applications.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Naito et al. (US 2018/0366548 A1; hereinafter referred to as Naito) in view of Naito et al. (US 2016/0035868 A1; hereinafter referred to as Naito_868).
Regarding 5, Naito discloses the semiconductor device according to claim 1. Naito does not disclose
wherein a length of the emitter region in the trench extending direction is equal to or greater than 0.5 times and equal to or smaller than ten times a length of the contact region in a trench extending direction.
Naito_868 discloses an IGBT semiconductor device, and is therefore analogous art, specifically Naito_868 teaches ([0060], also fig. 1)
wherein a length (W1) of the emitter region (6) in the trench extending direction (fig 1) is equal to or greater than 0.5 times and equal to or smaller than ten times a length (W2) of the contact region (7) in a trench extending direction (fig 1, “W1 in the first direction … 0.6 μm or more, 1.41 μm or less” ([0060] ln 03-09), “W2 in the first direction … 1.8 μm or more, 4.21 μm or less” ([0060] ln 03-09). Examiner interprets length (W1) of emitter region, range of reference is 0.6-1.41 μm, to be equal or greater than 0.5 times length (W2) of contact region, range of reference 1.8-4.21 μm by showing one example as follows: 0.5 x W2(1.8 μm) = 0.9 μm, which is within range of reference 0.6-1.41 μm for the length (W1) of emitter region).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize an emitter region and contact region as disclosed by Naito and to include an emitter region that is greater than 0.5 times greater in length than the contact region as taught by Imagawa because in power semiconductor devices, emitter regions and contact region dimensions are chosen to maximize efficiency and reliability. For example, a smaller, highly doped emitter concentrates current injection, while a larger, lightly doped emitter minimizes ohmic resistance, reduces heat density, and prevents thermal runaway by efficiently dissipating heat.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Naito et al. (US 2018/0366548 A1; hereinafter referred to as Naito) in view of Kyogoku et al. (US 10,199,466 B1; hereinafter referred to as Kyogoku).
Regarding claim 7, Naito discloses the semiconductor device according to claim 1. Naito does not disclose
wherein a doping concentration of the emitter region is equal to or greater than 2E19 cm-3 and equal to or smaller than 4E20 cm-3.
Kyogoku discloses a SiC MOSFET and IGBT (col 21, ln 38-44), and is therefore analogous art, specifically Kyogoku teaches
wherein a doping concentration (impurity concentration [col 7, ln 20-23) of the emitter region (source region 30a) is equal to or greater than 2E19 cm-3 and equal to or smaller than 4E20 cm-3 (“impurity concentration of … source region 30a … for example, 1x 10-19 cm-3 or more” [col 7, ln 20-23], examiner interprets that claimed that > 1x 10-19 cm-3 in reference addresses claimed range limitation.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize emitter regions as disclosed by Naito and to include emitter regions with a doping concentration greater than 1x 10-19 cm-3 as taught by Kyogoku because a higher doping in the emitter region injects more carriers into the device which increases the efficiency of device operation.
Claim 10-12 is rejected under 35 U.S.C. 103 as being unpatentable over Naito et al. (US 2018/0366548 A1; hereinafter referred to as Naito)
Regarding claim 10, Naito discloses the semiconductor device according to claim 1. Naito does not disclose
wherein the emitter region is provided to be spaced apart from the side wall of the first trench portion.
Naito’s other embodiment (fig 10B) which contains dummy trenches (without sources 12) discloses
wherein the emitter region (source 12, see annotated fig 10B below) is provided to be spaced apart from the side wall (SW1) of the first trench portion (TR1).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize emitter regions and trenches as discloses by Naito and to include emitter regions that are spaced apert from the trench sidewall as taught by Naito’s other embodiment because dummy cells are inserted into a design to improve yield. For example, certain annealing and etching steps in the manufacturing process work best on a relatively uniform surface, and inserting extra dummy cells into empty areas improves the uniformity and therefore the yield.
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Regarding claim 11, Naito discloses the semiconductor device according to claim 10. Naito further discloses
wherein the plurality of trench portions (30 and 40) include a dummy trench portion (30, “dummy trench portion 30” [0048] ln 02-03), and the first trench portion (TR1, see above annotated fig 10B in claim 10, examiner interprets that TR1 is the first dummy trench going left to right in annotated fig 10B) is the dummy trench portion (30).
Regarding claim 12, Naito discloses the semiconductor device according to claim 10. Naito further discloses
wherein the first trench portion (TR1G, see above annotated fig 10B in claim 10, examiner interprets that TR1G is the first gate trench going right to left in annotated fig 10B) is the gate trench portion (40).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Naito et al. (US 2018/0366548 A1; hereinafter referred to as Naito) in view of Noborio et al. (US 2023/0065815 A1; hereinafter referred to as Noborio).
Regarding claim 16, Naito discloses the manufacturing method of a semiconductor device according to claim 15. Naito does not disclose
wherein the contact region is formed by an ion implantation using the same mask as that of the base region.
Noborio teaches a method of manufacturing a SiC MOSFET and IGBT ([0116] ln 09) and is therefore analogous art, specifically Noborio teaches (fig 4I)
wherein the contact region (3a) is formed by an ion implantation (“ion-implanted” [0086] ln 04) using the same mask (“mask … is placed on the base region 3 … and impurity is ion-implanted … to form the contact region 3a” [0086] ln 03-04) as that of the base region (3).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize a contact region and a base region as disclosed by Naito and to include a lithography mask that can be utilized on both a contact region and a base region as taught by Noborio because utilizing the same masks for multiple implantations reduces the mask quantity which reduces the overall cost of a lithography mask set.
Allowable Subject Matter
Claims 6, 8 and 13-14, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device:
comprising an interlayer dielectric film provided above the front surface of the semiconductor substrate and including a contact hole, wherein a terminating position of the emitter region in the trench array direction is below the contact hole.
Regarding claim 8, the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device:
wherein in a depth direction of the semiconductor substrate, a thickness of the contact region is smaller than a thickness of the emitter region.
Regarding claim 13, the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device:
wherein the contact region is provide from an end portion of the first emitter region to the side wall of the first trench portion in the trench array direction, and provided from an end portion of the second emitter region to the side wall of the gate trench portion, and the first emitter region and the second emitter region are alternately provided in the trench extending direction.
Claim 14 depends from claim 13, and therefore, are allowable for the same reason as claim 13.
Regarding claim 17, the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a manufacturing method:
wherein the emitter region is formed, after forming the contact region, by an implantation to invert a polarity of a region of the second conductivity type to a region of the first conductivity type.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN OSCAR RIVAS whose telephone number is (571)272-5529. The examiner can normally be reached M-F 0900-0500.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rafael Perez-Gutierrez, can be reached on 571-272-7915. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R./
Examiner, Art Unit 2642
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812