DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 8-13) in the reply filed on 10/08/2025 is acknowledged. Non-elected claims 1-7, 14-20 are withdrawn from consideration. Thus, claims 8-13 are presented for examination. Applicant's election with traverse is addressed in the Response to Arguments section.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8, 12 and 13 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated Biederman et al (US Publication 20220337683 A1).
Regarding claim 8, Biederman discloses an electronic device comprising a time management unit for use in a synchronous electronic system, wherein the time management unit [Fig. 1] comprises:
a main timer [main timer 102] for storing a number of bits indicating a time [main timer 102];
a residual timer [time translator 104] for storing additional bits [correction table/look up] indicating lower significant digits of the time [0035-0036] [0042: The network interface device can access time domain information and parameters from correction table 306 to translate a time stamp from main timer domain to time domain of a host] [Fig. 3, shows the correction table 306 stored in the time translator 304];
digital circuitry coupled to the main timer and the residual timer [0035-0036] [0042: The network interface device can access time domain information and parameters from correction table 306 to translate a time stamp from main timer domain to time domain of a host]; and
a digital output designed to output time information from the main timer to a serial bus [0025] [0027-0028] [0035-0036] [0040] [0042: Time translation 304 and/or MAC parser 302 can convert the packet arrival time stamp from a first time domain to a second time domain. The network interface device can access time domain information and parameters from correction table 306 to translate a time stamp from main timer domain to time domain of a host] [0079: system 1200 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others… buses can include serial bus].
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Regarding claim 12, Biederman discloses the electronic device of claim 8, further comprising a counter coupled to the digital circuitry [0037, 0043, 0058, 0067: counter].
Regarding claim 13, Biederman discloses the electronic device of claim 8, further comprising additional processing circuitry configured to generate data to be communicated with a target electronic device that will process the data synchronously with a clock that uses the time information [0016, 0017,0048,0057: synchronization between different time domains with time information].
Allowable Subject Matter
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, the prior arts of record do not disclose “wherein the digital circuitry is designed to: detect whether a time correction is needed; in response to detecting that a time correction is not needed, update the main timer by a clock period; and in response to detecting that a time correction is needed, update the main timer by a clock period and a correction value from the residual timer.” incorporated with other limitations as claimed in claim 8.
Claims 10-11 are objected to allow because their dependency on claim 9.
Response to Arguments
Applicant’s election with traverse of Group I, claims 8 - 13 in the reply filed on 10/08/2025 is acknowledged. The traversal is on the ground(s) that the restriction requirement fails to provide a proper basis for combination/sub combination restriction and fails to demonstrate a serious search burden as required by the MPEP. This is not found persuasive because the limitations recited in each Group I, II and III are directed to different inventions. The differences in each claimed Group I, II and III are presented at least in a table below.
Group I
Group II
Group III
1. A method of operating an electronic device, the method comprising:
generating an initial time value; generating an initial time stamp based on the initial time value, the initial time stamp having a number of bits;
transmitting the initial time stamp from the electronic device; for a set period of time: updating the time stamp; transmitting the updated time stamp from the electronic device; and after the set period of time: adjusting the updated time stamp by a residual time amount; and transmitting the adjusted time stamp from the electronic device.
8. An electronic device comprising a time management unit for use in a synchronous electronic system, wherein the time management unit comprises:
a main timer for storing a number of bits indicating a time; a residual timer for storing additional bits indicating lower significant digits of the time;
digital circuitry coupled to the main timer and the residual timer; and
a digital output designed to output time information from the main timer to a serial bus.
14. A method of operating an electronic system that comprises a host device and a target device, the method comprising:
initializing a digital time stamp of the host device based on a system clock of the host device;
transmitting the digital time stamp from the host device to the target device; repeatedly performing the steps of: incrementing a counter; detecting whether a time correction is needed based on the counter; in response to detecting that the time correction is not needed, updating the digital time stamp by a clock period only and transmitting the updated digital time stamp from the host device to the target device; and in response to detecting that the time correction is needed, updating the digital time stamp by a clock period and a correction value, transmitting the updated digital time stamp from the host device to the target device, and resetting the counter.
As presented in the table above, Group I is directed to a method of operating an electronic device with the limitations (Ax) “transmitting the initial time stamp from the electronic device; for a set period of time: updating the time stamp; transmitting the updated time stamp from the electronic device; and after the set period of time: adjusting the updated time stamp by a residual time amount; and transmitting the adjusted time stamp from the electronic device” are not recited neither Group II nor Group III.
Group II is directed to an electronic device comprising a time management unit for use in a synchronous electronic system, with the limitations (By) “the time management unit comprises a main timer for storing a number of bits indicating a time; a residual timer for storing additional bits indicating lower significant digits of the time; digital circuitry coupled to the main timer and the residual timer; and a digital output designed to output time information from the main timer to a serial bus” are not recited in neither Group I nor Group III.
Group III is directed to a method of operating an electronic system comprises a host device and a target device with the limitations (Cz) “initializing a digital time stamp of the host device based on a system clock of the host device; transmitting the digital time stamp from the host device to the target device; repeatedly performing the steps of: incrementing a counter; detecting whether a time correction is needed based on the counter; in response to detecting that the time correction is not needed, updating the digital time stamp by a clock period only and transmitting the updated digital time stamp from the host device to the target device; and in response to detecting that the time correction is needed, updating the digital time stamp by a clock period and a correction value, transmitting the updated digital time stamp from the host device to the target device, and resetting the counter” are not recited in Group I and Group II.
According to MPEP § 809.02(a) states that restriction for examination purposes as indicated is proper because all these inventions in Group I, II and III are independent or distinct for the reasons given above and there would be a serious search and examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification; (b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter; (c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); (d) the prior art applicable to one invention would not likely be applicable to another invention; (e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
In summary, different inventions in group I, II and III requires a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries) and the prior art applicable to one invention would not likely be applicable to another invention. For example, the search queries and prior arts used for limitations (Ax) in Group I are different from Group II and Group III. Similarly, the search queries and prior arts used for limitations (By) in Group II are different from Group I and Group III. Lastly, the search queries and prior arts used for limitations (Cz) in Group III are different from Group I and Group II.
On page 7 of the Office Action, Applicant states that Group I’s method claims 1 and 2 “adjusting the updated time stamp by a residual time amount” and “updating a residual time by quantization error amount” require the specific correction mechanism cited in Group II’s apparatus (main timer, residual timer, digital circuitry). Examiner respectfully disagrees because none of the correction mechanism in Group II’s apparatus (main timer, residual timer, digital circuitry) nor Group’s III method are required to perform the steps recited above “adjusting the updated time stamp by a residual time amount” and “updating a residual time by quantization error amount” in Group I.
As explained above, Examiner points out different scopes for each Group I, II and III. Thus, each group is directed to different invention, different search queries and different prior art(s). Applicant’s argument on the traversal could be persuasive if Applicant can show how the claimed limitations/or claimed scope from Group I, II, and III are directed to the same invention or could be rejected using the same prior arts.
For all of the foregoing reasons above, Examiner submits that Applicant’s argument is not persuasive and the restriction requirement is still deemed proper and is therefore made FINAL.
Pertinent Arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rozario (US Patent 7352748) discloses an address entry stored in a table within egress on-chip memory 222 includes timer bits 638 and delayed update bits 640 [Col. 11 lines 36-50].
Bordogna (US Patent 12222750 B2) A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain [abstract].
Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176