Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant’s Amendments / Arguments Regarding 35 U.S.C. §102/ 103
The applicant’s remarks, on pages 5-7 of the response / amendment, the applicant argues the features which allegedly distinguish over the previously cited references cited in the 35 U.S.C. §102/ 103 rejections.
Applicant’s arguments have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-7, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 20170329976 to Minamikawa (hereinafter Minamikawa), in view of US 20230393739 to Binfet et al. (hereinafter Binfet).
Regarding claim 1, Minamikawa teaches,
A data protection device, comprising: (figs. 1-2)
a memory; ([0012] RAM 12 of figs. 1-2.)
a read-only memory, ([0012] ROM 13 and SEEPROM 15 of fig. 2) storing first confidential data, and transmitting the first confidential data to the memory after being powered up, wherein the first confidential data comprises ([0031] teaches TPM access key (“first confidential data”) in information 150 in SEEPROM 15 of fig. 2. [0025] teaches that the TPM must be ready to use (initialization state) )
a verification circuit, determining whether the first confidential data is valid before a processor reads the first confidential data from the memory, (fig. 2, TPM access key 41 in SD Card.) and allowing the processor to read the first confidential data from the memory when the first confidential data is valid. ([0031] teaches comparing TPM access key 41 in SD Card 4 with TPM access key in information 150. [0035] teaches decryption unit reads out. [0060] teaches that S23 of fig. 4 decryption succeeds, then other processes may be performed. See also, Abstract.) (Alternatively, if the key verification procedures (in [0031-32]) fail, then [0034] teaches when verification of the EDEK fails, operation stop unit 101 stops subsequent operations, as discussed in the rejection of claim 5.)
Minamikawa fails to explicitly teach storing / using more than two groups of repetitive data,
However, Binfet teaches,
wherein the first confidential data comprises more than two groups of repetitive data and the groups of repetitive data are the same with one another; and (Abstract teaches data stored in a plurality of copies of the data, where error correction is performed by comparing the plurality of copies to determine a dominant copy of the bits of the data., [0028-29] teaches multiple redundant copies of the data, where there are 8 or 16 redundant copies, and [0029] teaches error correction to determine the dominant state of each bit, using bit majority / dominant state of the bits. See also, fig. 2 & [0039] which teaches using dominant bit state of the plurality of copies to error correct.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Minamikawa, which teaches verifying confidential data (encryption key) using another memory that includes the same confidential data by comparing the values (Abstract & [0031-35]), with Binfet, which also teaches the use of multiple redundant copies of data to detect errors (Abstract & [0028-29]), and additionally teaches the use of 8 or 16 redundant copies of data for the error detection and correction using the dominant state of the bits ([0028-29]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Minamikawa with the added ability to use 8 or 16 copies of the data to detect an error and using the dominant state of the bits to restore the data to an error free state, as taught by Binfet, for the purpose of increasing security and increasing computational efficiency by reducing or eliminating errors in the data.
Regarding claim 2, Minamikawa and Binfet teach,
The data protection device according to claim 1,
wherein the verification circuit determines whether a same bit in each of the groups of repetitive data all has a same logical value to determine whether the first confidential data is valid. (Minamikawa, [0031] teaches “second verification unit 112 acquires the TPM access key 41 included in backup data from the SD card 4 and compares the TPM access key 41 with a TPM access key generated from the apparatus specific information 150 to thereby verify the validity of the TPM access key 41 in accordance with whether or not both the keys conform to each other.”)
Regarding claim 6, Minamikawa and Binfet teach,
The data protection device according to claim 1,
wherein the read-only memory further stores second confidential data, the second confidential data does not comprise a plurality of groups of second repetitive data, and the verification circuit does not verify whether the second confidential data is valid. (Minamikawa, fig. 2, SEEPROM 15 and [0026] teach that the SEEPROM may store other information than the key information.)
Regarding claim 7, Minamikawa and Binfet teach,
The data protection device according to claim 6,
wherein a data size of the second confidential data is less than a data size of the first confidential data. (Minamikawa, fig. 2, SEEPROM 15 and [0026] teach that the SEEPROM may store other information than the key information, where apparatus specification information could include a serial number that would be smaller than a standard 128 or 256 bit encryption key.)
Regarding claim 9, Minamikawa and Binfet teach,
The data protection device according to claim 1, wherein the first confidential data comprises a key used for encryption/decryption. (Minamikawa, Abstract, teaches verifying the encryption key. Fig. 2 and [0031-33] teaches the data being verified is the encryption / decryption key.)
Regarding claim 10, Minamikawa and Binfet teach,
The data protection device according to claim 1, wherein the read-only memory transmits the first confidential data to the memory before the processor starts to operate. (Minamikawa, [0031-34] teach the SEEP ROM transmitting the key, then the key verification occurs, and after key verification is successful, [0060] teaches subsequent processes can be continuously performed.)
Regarding claim 11, Minamikawa and Binfet teach,
A data protection method applied to a data protection device, the data protection method comprising:
after the data protection device is powered up, transmitting first confidential data to a memory by a read-only memory, wherein the first confidential data comprises more than two groups of repetitive data and the groups of repetitive data are same with one another;
before a processor reads the first confidential data from the memory, determining whether the first confidential data is valid according to the groups of repetitive data in the first confidential data; and
allowing the processor to obtain the first confidential data from the memory when the first confidential data is valid.
Claim 11 is rejected using the same basis of arguments used to reject claim 1 above.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Minamikawa, in view of Binfet, in view of US 20050015649 to Lee et al. (hereinafter Lee).
Regarding claim 3, Minamikawa and Binfet teach,
The data protection device according to claim 1,
wherein the verification circuit determines whether a same bit in each of the groups of repetitive data all has a first logical value and determines whether the same bit in each of the groups of repetitive data all has a second logical value to determine whether the first confidential data is valid, wherein the first logical value is (Minamikawa, [0031] teaches “second verification unit 112 acquires the TPM access key 41 included in backup data from the SD card 4 and compares the TPM access key 41 with a TPM access key generated from the apparatus specific information 150 to thereby verify the validity of the TPM access key 41 in accordance with whether or not both the keys conform to each other.”)
Minamikawa and Binfet fail to teach comparing values that are different from one another in the verification,
However, Lee teaches,
wherein the verification circuit determines whether a same bit in each of the groups of repetitive data all has a first logical value and determines whether the same bit in each of the groups of repetitive data all has a second logical value to determine whether the first confidential data is valid, wherein the first logical value is different from the second logical value. (fig. 2 teaches multiple segments 1-N that may be verified with a single correction segment, using the check value (e.g., check sum), XORing the segments 1-N, and comparing the XORed values to the correction segment to identify the incorrect bit(s), as discussed in [101-104]. See also, [0047-48] and [0062-63].)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Minamikawa, which teaches verifying confidential data (encryption key) using another memory that includes the same confidential data by comparing the values (Abstract & [0031-35]), with Binfet, which also teaches the use of multiple redundant copies of data to detect errors (Abstract & [0028-29]), and additionally teaches the use of 8 or 16 redundant copies of data for the error detection and correction using the dominant state of the bits ([0028-29]), with Lee, which also teaches verifying that a memory has not been corrupted by comparing to a correction segment (fig. 2), and additionally teaches comparing values in multiple memory segments (segments 1-N of fig. 2) and also using check value 11, to identify a segment with bad data, and performing XOR operations on the other data, and comparing with a correction segment (fig. 2), to correct the segment with bad data. One of ordinary skill in the art would have been motivated to perform such an addition to provide Minamikawa and Binfet with the added ability to increase security by also performing data verification but utilizing a smaller memory (1 correction segment for N segments), as taught by Lee, for the purpose of maintaining the security Minamikawa and decreasing the need for memory, as taught by Lee.
Regarding claim 4, Minamikawa, Binfet, and Lee teach,
The data protection device according to claim 3, wherein when the same bit in the groups of repetitive data all has the first logical value, the verification circuit sets the same bit to the first logical value. (Minamikawa, [0031-35] teaching the keys being compared during verification.) (Lee, fig. 2 and [0101-104] where the correction segment is set according to the bits in the segments 1-N using XOR.)
Regarding claim 5, Minamikawa, Binfet, and Lee teach,
The data protection device according to claim 3,
wherein when the same bit does not all have the first logical value or does not all have the second logical value, the verification circuit determines the first confidential data to be invalid, and issues an interrupt request to the processor. (Minamikawa, fig. 2 and [0034] teach when verification of the EDEK fails, operation stop unit 101 stops subsequent operations.) (Lee, fig. 2 and [0101-102] teaching detecting a single bit of error in multiple (data) segments using the correction segment.)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Minamikawa, in view of Binfet, in view of US 20230042857 to Nesargi et al. (hereinafter Nesargi).
Regarding claim 8, Minamikawa and Binfet teach,
The data protection device according to claim 1,
wherein the verification circuit further verifies whether the first confidential data is valid (Minamikawa, [0031] teaches the verification of the access key in SEEPROM 15, at 150 with the key 41. [0060] teaches the verification being successful before other processes are performed. This would include using the key.)
Minamikawa and Binfet fail to explicitly teach verification of data before sending the data,
However, Nesargi teaches,
wherein the verification circuit further verifies whether the first confidential data is valid before the read-only memory transmits the first confidential data to the memory. ([0007] teaches validating data before sending the validated data.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Minamikawa, which teaches verifying confidential data (encryption key) using another memory that includes the same confidential data by comparing the values (Abstract & [0031-35]), with Binfet, which also teaches the use of multiple redundant copies of data to detect errors (Abstract & [0028-29]), and additionally teaches the use of 8 or 16 redundant copies of data for the error detection and correction using the dominant state of the bits ([0028-29]), with Nesargi, which also teaches verifying data ([0007]), and additionally teaches verifying the data before sending the data to another location. One of ordinary skill in the art would have been motivated to perform such an addition to provide Minamikawa and Binfet with the added ability to perform verification on data before sending the data to another location, as taught by Nesargi, for the purpose of increasing security by preventing the use of unverified data and thus, increasing computational efficiency.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FARID HOMAYOUNMEHR/Supervisory Patent Examiner, Art Unit 2495