DETAILED ACTION
This Office action is in response to the application filed on 26 December 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 12 and 18 are objected to because of the following informalities:
In claim 12 at line 2, “a relative voltage” should be changed to “the relative voltage”.
In claim 18 at line 7, “an absolute voltage”1 should be changed to “the absolute voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mok et al. (US 2009/0079401; hereinafter “Mok”).
In re claim 1, Mok discloses a voltage converter (Fig. 2) configured to provide an output voltage (voltage at node between L and rC), the voltage converter comprising:
a first device (ADC0 240), configured to measure an absolute voltage with respect to a reference voltage (see [0032]; that is, ADC0 240 measures the output voltage; since Mok does not specify that the output voltage is referenced to any other voltage in the circuit, it is presumed as a matter of convention that it is referenced to ground); and
a second device (ADC2 235), configured measure a relative voltage with respect to the absolute voltage (the term “relative voltage” is understood according to Applicant’s specification, and as such, ADC2 235 is considered as measuring a relative voltage in that it measures the instantaneous output voltage at a faster sampling rate than ADC0 240: see [0033]);
such that the output voltage is regulated using the measurements of the absolute voltage and the relative voltage (the output voltage is measured using circuit blocks 215, 220, and 225, taking into account the outputs of both ADC0240 and ADC2 235: see [0033] and [0036]-[0037]).
In re claim 2, Mok discloses wherein the voltage converter is one of a buck converter, a boost converter, a buck-boost converter or an integrated voltage regulator (see Fig. 2 and [0018]).
In re claim 3, Mok discloses wherein the first device (ADC0 240) is configured to measure the absolute voltage at a first sampling rate ([0032]).
In re claim 4, Mok discloses wherein the first sampling rate is a pre-determined rate (see end of [0034]: the first sampling rate is a fixed rate, considered equivalent to pre-determined).
In re claim 5, Mok discloses wherein the absolute voltage is the instantaneous output voltage sampled at the first sampling rate with respect to the reference voltage (see [0032], and see the note with respect to claim 1 above, that the measured voltage is presumed as a matter of convention to be referenced to ground).
In re claim 6, Mok discloses wherein the reference voltage is a ground voltage (see note with respect to claim 5, above).
In re claim 7, Mok discloses wherein the absolute voltage is compared to a target output voltage for the voltage converter (see combiner 250 in Fig. 2 and see [0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Mok in view of Fosler (US 2007/0085720).
In re claim 8, Mok discloses the invention according to claim 7 as explained above, and further discloses that the first device comprises an analog-to-digital controller (see Fig. 2: ADC0 240). Mok does not disclose that the ADC is coupled to a clock counter, such that the clock counter sets the first sampling rate.
Whereas it was basic knowledge in the art that an ADC circuit, being a component of digital circuitry, uses a clock signal to set a sampling rate. An example of this is shown in Fosler, disclosing a digital controller for a voltage converter (see Fig. 4), comprising an ADC (408) for measuring an absolute output voltage (from VSENSE), wherein the ADC (408) is coupled to, and receives a clock signal from, a clock counter (see Fig. 5, showing ADC 408 receiving clock signal ADCCK, and Fig. 6, showing ADCCK being provided from clock counter circuitry including 618, 620, 626, 624), thus enabling the ADC to perform its primary functionality in the expected and conventional manner (see, e.g., [0059]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltage converter of Mok by coupling the ADC of the first device to a clock counter, such that the clock counter sets the first sampling rate, as this represents the conventional manner of implementation of an ADC, as shown by Fosler. The use of the clock counter to set the first sampling rate would enable the ADC to perform its expected operations in a conventional manner.
In re claim 9, Mok does not disclose wherein the second device comprises: a sample-and-hold circuit coupled to the clock counter; and a comparison circuit.
Whereas Fosler discloses the conventional implementation of an ADC (see, e.g., Figs. 7 and 10) including a sample-and-hold (S&H) and comparison circuit (Figs. 7, 10: comparators 740 each include an S&H section performed by switches 1010-1016 and comparison section 1004, 1030; see [0071], [0088]). Fosler teaches that these circuits enable the ADC to function as a window flash ADC for measuring a window or difference voltage, or in other words a relative voltage, as opposed to an absolute voltage ([0076]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the voltage converter of Mok by implementing the ADC of the second device to comprise a sample-and-hold circuit coupled to the clock counter; and a comparison circuit, as shown by Fosler, in order to obtain the functionality of accurately measuring the relative voltage as opposed to the absolute voltage.
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 10-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 10, the closest prior art of record is the combination of Mok and Fosler as presented above in this Office action with respect to claim 9. However, this combination of references does not provide a teaching of using the sample-and-hold circuit of the second device to measure the abolute voltage at the first sampling rate. That is, MOK specifically teaches the second device sampling at the second, higher sampling rate, as compared to the first, lower sampling rate used by the first device.
Claims 11-17 each depend, either directly or indirectly, from claim 10 and would therefore be allowable for the same reasons as explained above.
With respect to claim 18, the closest prior art is the Mok reference, cited above in this Office action. Mok discloses a method of regulating an output voltage of a voltage converter, this method being embodied as the functional operation of the cited circuitry of Fig. 2. As such, Mok discloses measuring an absolute voltage at a first sampling rate; comparing the absolute voltage to a reference voltage to generate a first error voltage; measuring a relative voltage at a second sampling rate, the second sampling rate being faster than the first sampling rate, as was cited and explained above with respect to the rejections of claims 1-7.
However, Mok as the closest prior art does not disclose comparing the relative voltage to an absolute voltage to generate a second error voltage; and generating a control signal configured to regulate the output voltage of the voltage converter, such that the control signal is based on the first error voltage and the second error voltage. That is, Mok provides the measured relative voltage to a transient recovery controller (225) for detecting a rapid slope change of the output voltage (see [0029]), rather than the claimed solution, recited in claim 18, of comparing the relative voltage to the absolute voltage to generate a second error signal and regulating the output voltage based on both the first and second error signals.
Claims 19-20 each depend, either directly or indirectly, from claim 18 and would therefore be allowable for the same reasons as explained above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2004/0095112 discloses a power converter circuitry and method for digital control of a voltage converter using clocked ADCs to measure absolute and relative voltages.
US 2014/0333270 discloses digital control of a voltage converter including the measurement of relative and absolute voltages using ADCs.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 It is noted that the reference to “absolute voltage” at line 7 of claim 18 is considered to be the same voltage as that introduced in line 3 and referred to again at line 4. This is further evidenced by the fact that dependent claim 19 also refers to “the absolute voltage,” signaling that there is just one absolute voltage being defined by the claims.