CTNF 18/396,071 CTNF 86916 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia In the present application, filed on or after March 16, 2013, claims 1-4 have been considered and examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election of Group I, claims 1-4 in the reply on April 06, 2026 is acknowledged. Because Applicant failed to distinctly and specifically point out supposed errors in the restriction requirement, Applicant's election of Group I, claims 1-4 has been treated as an election without traverse (MPEP §818.03(b)). Claims 5-6 are withdrawn as being directed to non-elected invention. The election requirement is made final. Information Disclosure Statement The information disclosure statements (IDS) submitted on 12/26/2023, 10/25/2024, 12/02/2024, 05/28/2025, 03/27/2026 are in compliance with the provision of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by Examiner, except for the NPL without English translations or the foreign documents because Examiner was not able to locate the above documents. Double Patenting 08-33 The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717 .02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.32l(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http ://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.jsp. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 1-4 are rejected on the ground of nonstatutory double patenting over claims 1-16 of the patent US 11,893,435 B2 since the claims, if allowed, would improperly extend the "right to exclude" already granted in the patent. The subject matter claimed in the instant application is fully disclosed and covered the patent US 11,893,435 B2 , as follows: Claim US 18/396,071 Claim US 11,893,435 B2 1 An internal voltage generation circuit of a smart card configured to perform a fingerprint authentication, the internal voltage generation circuit comprising: 1 An internal voltage generation circuit of a smart card configured to perform a fingerprint authentication, the internal voltage generation circuit comprising: 1 a first contact switch configured to selectively switch a contact voltage received from an external card reader to a first node based on a first switching enable signal, in a contact mode; 1 a first contact switch configured to selectively switch a contact voltage received from an external card reader to a first node based on a first switching enable signal, in a contact mode; 1 a second contact switch configured to selectively switch the contact voltage to a second node based on a second switching enable signal, in the contact mode; 1 a second contact switch configured to selectively switch the contact voltage to a second node based on a second switching enable signal, in the contact mode; 1 a switched capacitor converter configured to step down a contactless voltage induced from an electromagnetic wave received from the card reader to provide a first voltage to the first node in a contactless mode; 1 a switched capacitor converter configured to step down a contactless voltage induced by an electromagnetic wave received from the card reader to provide a contactless mode first driving voltage to the first node; 1 a bidirectional switched capacitor converter, connected to the first node and the second node, the bidirectional switched capacitor converter configured to: 1 a bidirectional switched capacitor converter, connected to the first node and the second node, the bidirectional switched capacitor converter configured to: 1 step down a first driving voltage of the first node to provide a second voltage to the second node in the contactless mode; and 1 in a contactless mode, step down the contactless mode first driving voltage at the first node to provide a contactless mode second driving voltage to the second node; and 1 either step down the first driving voltage or boost a second driving voltage of the second node based on a level of the contact voltage to provide a boosted voltage to the first node; 1 in the contact mode, either step down a contact mode first driving voltage at the first node to provide a contact mode second driving voltage to the second node, or boost a contact mode second driving voltage at the second node based on a level of the contact voltage to provide a boosted voltage to the first node; 1 a mode selector configured to output a first mode signal and a second mode signal, 1 a mode selector configured to output a first mode signal and a second mode signal, 1 the first mode signal designating one of the contact mode and the contactless mode, the second mode signal designating one of sub-modes of the contact mode, the mode selector further configured to select a highest voltage from among the contact voltage, the contactless voltage and the first driving voltage and output the selected voltage as a control voltage; and 1 the first mode signal designating one of the contact mode and the contactless mode, the second mode signal designating one of a plurality of sub-modes of the contact mode, the mode selector further configured to select a highest voltage among the contact voltage, the contactless voltage and the contactless mode first driving voltage or the contact mode first driving voltage to output the selected voltage as a control voltage; and 1 a control signal generator configured to generate a first power-down signal, a second power-down signal, the first switching enable signal and the second switching enable signal based on the first mode signal and the second mode signal, 1 a control signal generator configured to generate a first power-down signal that enables/disables the switched capacitor converter, a second power-down signal that enables/disables the bidirectional switched capacitor converter, the first switching enable signal and the second switching enable signal, based on the first mode signal and the second mode signal. 1 wherein the first contact switch includes: 8 wherein the first contact switch includes: 1 a main switch including a first p-channel metal-oxide semiconductor (PMOS) transistor which has a source coupled to the contact voltage and a drain coupled to the first node; and 8 a main switch including a first p-channel metal-oxide semiconductor (PMOS) transistor which has a source coupled to the contact voltage and a drain coupled to the first node; 1 an assist switch including a second PMOS transistor which has a source coupled to a gate of the main switch as a first internal node, a drain coupled to the contact voltage and a gate receiving an on-voltage associated with generating the control voltage, and 8 an assist switch including a second PMOS transistor which has a source coupled to a gate of the main switch at a first internal node, a drain coupled to the contact voltage and a gate receiving an on-voltage associated with generating the control voltage; 1 wherein the assist switch is configured to be turned-on in response to the on-voltage before the control voltage is generated and is configured to prevent overcurrent flowing into the main switch. 9 wherein the assist switch is configured to be turned-on in response to the on-voltage before the control voltage is generated and is configured to prevent overcurrent flowing into the main switch Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (B) CONCLUSION – The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112(pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 AIA Claim s 1-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre- AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites “the contact voltage at respective levels corresponding to a class associated with a level of the contact voltage in a contact mode.” It is not clear whether the contact voltage has a respective level or multiple respective levels associated a class of the external card reader or a class of the smart card. Claims 2-3 are rejected because of being dependent on a rejected claim 1 . Reasons for Allowance The following is an examiner’s statement of reasons for allowance: claim 4 is allowable because prior art fails to teach or suggest the claimed invention in combination. While most of individual limitation, having components and functions, are generically and separately known in the art, the combination of all of the components and their interactions are not sufficiently taught in the prior art in the claimed manner, and the Examiner can find no motivation to combine or modify the references of record without the use of impermissible hindsight including an internal voltage generation circuit of a smart card configured to perform a fingerprint authentication, the internal voltage generation circuit comprising: a first contact switch configured to selectively switch a contact voltage received from an external card reader to a first node based on a first switching enable signal, in a contact mode ; a second contact switch configured to selectively switch the contact voltage to a second node based on a second switching enable signal, in the contact mode; a switched capacitor converter configured to step down a contactless voltage induced from an electromagnetic wave received from the card reader to provide a first voltage to the first node in a contactless mode; a bidirectional switched capacitor converter, connected to the first node and the second node, the bidirectional switched capacitor converter configured to: step down a first driving voltage of the first node to provide a second voltage to the second node in the contactless mode; and either step down the first driving voltage or boost a second driving voltage of the second node based on a level of the contact voltage to provide a boosted voltage to the first node; a mode selector configured to output a first mode signal and a second mode signal, the first mode signal designating one of the contact mode and the contactless mode, the second mode signal designating one of sub-modes of the contact mode, the mode selector further configured to select a highest voltage from among the contact voltage, the contactless voltage and the first driving voltage and output the selected voltage as a control voltage; and a control signal generator configured to generate a first power-down signal, a second power-down signal, the first switching enable signal and the second switching enable signal based on the first mode signal and the second mode signal, wherein the first contact switch includes: a main switch including a first p-channel metal-oxide semiconductor (PMOS) transistor which has a source coupled to the contact voltage and a drain coupled to the first node; and an assist switch including a second PMOS transistor which has a source coupled to a gate of the main switch as a first internal node, a drain coupled to the contact voltage and a gate receiving an on-voltage associated with generating the control voltage, and wherein the assist switch is configured to be turned-on in response to the on-voltage before the control voltage is generated and is configured to prevent overcurrent flowing into the main switch. Citation of Pertinent Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure : Finn et al., US 12,159,180 B1, discloses RFID enabled metal transaction cards with coupler coil couplings and related methods. Mathieu et al., US 2022/0215220 A1, discloses biometric sensor module for a smart card and method for manufacturing such a module. Kollig et al., US 2021/0256338 A1, discloses biometric interface. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUANG PHAM whose telephone number is (571)-270-3668. The examiner can normally be reached 09:00 AM - 05:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, QUAN-ZHEN WANG can be reached at (571)-272-3114. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /QUANG PHAM/Primary Examiner, Art Unit 2685 Application/Control Number: 18/396,071 Page 2 Art Unit: 2685 Application/Control Number: 18/396,071 Page 3 Art Unit: 2685 Application/Control Number: 18/396,071 Page 4 Art Unit: 2685 Application/Control Number: 18/396,071 Page 5 Art Unit: 2685 Application/Control Number: 18/396,071 Page 6 Art Unit: 2685 Application/Control Number: 18/396,071 Page 7 Art Unit: 2685 Application/Control Number: 18/396,071 Page 8 Art Unit: 2685 Application/Control Number: 18/396,071 Page 9 Art Unit: 2685 Application/Control Number: 18/396,071 Page 10 Art Unit: 2685 Application/Control Number: 18/396,071 Page 11 Art Unit: 2685 Application/Control Number: 18/396,071 Page 12 Art Unit: 2685 Application/Control Number: 18/396,071 Page 13 Art Unit: 2685 Application/Control Number: 18/396,071 Page 14 Art Unit: 2685 Application/Control Number: 18/396,071 Page 15 Art Unit: 2685 Application/Control Number: 18/396,071 Page 16 Art Unit: 2685 Application/Control Number: 18/396,071 Page 17 Art Unit: 2685 Application/Control Number: 18/396,071 Page 18 Art Unit: 2685 Application/Control Number: 18/396,071 Page 19 Art Unit: 2685 Application/Control Number: 18/396,071 Page 20 Art Unit: 2685 Application/Control Number: 18/396,071 Page 21 Art Unit: 2685 Application/Control Number: 18/396,071 Page 22 Art Unit: 2685 Application/Control Number: 18/396,071 Page 23 Art Unit: 2685 Application/Control Number: 18/396,071 Page 24 Art Unit: 2685
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