DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-6, 9-11, 13-17, 19 and 20, with traverse, in the reply filed on 04/28/2026 is acknowledged. The traversal is on the ground(s) that search and examination of the entire application can be made without serious burden. This is not found persuasive because the species require a different field of search (e.g., searching different subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species; and/or the species are likely to raise different non-prior art issues under U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Claims 7, 12 and 18 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/28/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 9-10, 13, 16-17 & 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by RYU et al. (US 2022/0223732 A1)
Regarding claim 1, RYU teaches,
PNG
media_image1.png
510
668
media_image1.png
Greyscale
A semiconductor memory device (Fig. 10) comprising:
a bit line (conductive line 120 which may function as bit line, para [0030]) including a metal (para [0031]) and extending in a first direction (X) on a substrate (100, para [0028]);
a channel structure (130, para [0041]) on the bit line, the channel structure including a first channel pattern (including vertical portion of 130 on left) extending in a second direction (Z) , and
the channel structure including a second channel pattern (including vertical portion of 130 on right) spaced apart from the first channel pattern in the first direction (X) and extending in the second direction (Z);
a liner film (125, para [0093]) between the bit line and the channel structure, and the liner film including the metal (125 may include Titanium (Ti), para [0093]);
a first word line (150A, para [0045]) between the first channel pattern and the second channel pattern, and the first word line extending in the second direction (Z);
a second word line (150B) between the first channel pattern and the second channel pattern, the second word line extending in the second direction (Z), and the second word line spaced apart from the first word line in the first direction (X); and
a first capacitor (170A, para [0028]) and a second capacitor (170B, para [0028]) respectively on the first channel pattern and the second channel pattern, and connected to the first channel pattern and the second channel pattern(via landing pads 160A/160B).
Regarding claim 2, RYU teaches the semiconductor memory device of claim 1 and further teaches, wherein the liner film (125) extends along an upper surface of the bit line (120) (as seen in FIG. 10).
Regarding claim 3, RYU teaches the semiconductor memory device of claim 1 and further teaches , further comprising: a protruding insulating pattern (112, para [0028]) on the bit line, wherein the protruding insulating pattern and the liner film completely cover an upper surface of the bit line (FIG. 10).
Regarding claim 6, RYU teaches the semiconductor memory device of claim 1 and further teaches , further comprising: a protruding insulating pattern (112, para [0028]) on the bit line, wherein the first channel pattern includes a vertical part (vertical portion of 130 on left as marked ) extending along side walls of the protruding insulating pattern, and a horizontal part (horizontal part of 130 as marked below) extending along an upper surface of the liner film.
PNG
media_image2.png
510
668
media_image2.png
Greyscale
Regarding claim 9, RYU teaches the semiconductor memory device of claim 1 and further teaches , further comprising: a gate separation pattern (114, para [0028]) on the bit line, and separating the first word line and the second word line; and a connecting channel pattern (horizontal part of 130 as marked below) connecting the first channel pattern and the second channel pattern, wherein the connecting channel pattern is between the gate separation pattern and the liner film (as seen in Fig. 10 below).
PNG
media_image3.png
510
668
media_image3.png
Greyscale
Regarding claim 10, RYU teaches the semiconductor memory device of claim 1 and further teaches , wherein the channel structure includes indium gallium zinc oxide (130 may include indium gallium zinc oxide, para [0039]).
Regarding claim 13, RYU teaches,
A semiconductor memory device (FIG. 10) comprising:
a bit line (120], para [0030]) extending on a substrate (100, para [0028] in a first direction (X);
a protruding insulating pattern (112, para [0028]) on the substrate, the protruding insulating pattern including a channel trench (130t, Fig. 4, para [0034]) exposing the bit line (as seen in FIG. 4,130t formed on both sides of bit line 120 in direction Y and therefore exposing bit line 120 in direction Y, similar way CH_T exposing BL in direction D1 in FIG. 3 of the disclosure) it and
the protruding insulating pattern extending in a second direction (Z) intersecting the first direction (X);
a liner film (125, para [0093]) on an upper surface of the exposed bit line;
a channel structure (130, para [0041]) extending along a lower surface and side surface of the channel trench, and the channel structure including a first channel pat
tern (including vertical portion of 130 on left) and a second channel pattern (including vertical portion of 130 on right) spaced apart from the first channel pattern in the first direction (X);
a first word line (150A, para [0045]) and a second word line (150B, para [0045]) on the channel structure, and the first word line and the second word line spaced apart from each other in the first direction (X) and each extending in the second direction (Z);
a gate insulating film (140, para [0113]) between the first channel pattern and the first word line, and the gate insulating film between the second channel pattern and the second word line;
and a first capacitor (170A, para [0028]) and a second capacitor (170B, para [0028]) respectively on the first channel pattern and the second channel pattern, and the first capacitor and the second capacitor connected to the first channel pattern and the second channel pattern (via landing pads 160A/160B).
Regarding claim 16, RYU teaches the semiconductor memory device of claim 1 and further teaches , wherein the channel structure includes indium gallium zinc oxide (130 may include indium gallium zinc oxide, para [0039]).
Regarding claim 17, RYU teaches the semiconductor memory device of claim 1 and further teaches , wherein the channel structure includes a connecting channel pattern (horizontal part of 130 as marked below) connecting the first channel pattern and the second channel pattern, and the liner film is between the connecting channel pattern and the bit line (as seen below).
PNG
media_image3.png
510
668
media_image3.png
Greyscale
Regarding claim 19, RYU teaches the semiconductor memory device of claim 13 and further teaches , further comprising: a gate separation pattern (114, para [0028]) on the bit line, and separating the first word line and the second word line (as seen) , wherein the gate separation pattern overlaps the liner film in a third direction (Y).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 & 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. and further in view of Yu et al. (US 20220115393 A1)
Regarding claim 4, RYU teaches the semiconductor memory device of claim 1 but does not explicitly teach, wherein the liner film includes a nitride.
But RUU additionally teaches,
Contact line 125 between the conductive line 120 (bit line) and the channel layer 130 (see para [0092], Fig. 10) and may include metal material ( e.g. Ti, Ta) (see para [0093]).
Meanwhile, Yu teaches,
Channel contact HCP between bit line BL and cannel CH (Fig. 9) may include metal materials (e.g., copper or tungsten) and metal nitrides (e.g., TiN, TaN, or WIN) (para [0145]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute Ti (metal) with TiN (metal nitride) as a material for the contact line 125 (such that the liner film 125 includes a metal nitride (e.g. TiN), according to teaching of Yu, since the court has held that a simple substitution of one known element for another (metal nitride for metal) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). (Please see Smith v. Hayashi, 209 USPQ 754 (Bd. of Pat. Inter. 1980)).
Ordinary artisan would have been motivated to use metal nitride over metal as a contact line to channel in order to prevent unwanted silicide formation with metal during fabrication.
Regarding claim 14, RYU teaches the semiconductor memory device of claim 13 and further teaches , wherein the bit line (120) includes a first element (Ti, para [0031]), and the liner film (125) includes the first element (125 may include Ti, para [0093]),
But RUU does not explicitly teach,
and the linear film (125) includes a second element different from the first element.
But RUU additionally teaches,
Contact line 125 between the conductive line 120 (bit line) and the channel layer 130 (see para [0092], Fig. 10) and may include metal material ( e.g. Ti, Ta) (see para [0093]).
Meanwhile, Yu teaches,
Channel contact HCP between bit line BL and cannel CH (Fig. 9) may include metal materials (e.g., copper or tungsten) and metal nitrides (e.g., TiN, TaN, or WIN) (para [0145]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute Ti (metal) with TiN (metal nitride) as a material for the contact line 125 (such that the liner film 125 includes a second element (N) different from first element (Ti) , according to teaching of Yu, since the court has held that a simple substitution of one known element for another (metal nitride for metal) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). (Please see Smith v. Hayashi, 209 USPQ 754 (Bd. of Pat. Inter. 1980)).
Ordinary artisan would have been motivated to use metal nitride over metal as a contact line to channel in order to prevent unwanted silicide formation with metal during fabrication.
Regarding claim 15, RYU & Yoo teaches the semiconductor memory device of claim 14 and further teaches, wherein the second element includes nitrogen (second element includes nitrogen(N) as per claim 14 rejection above)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. and further in view of YOO et al. (US 2022/0216239 A1)
Regarding claim 11, RYU teaches the semiconductor memory device of claim 13 but does not explicitly teach, further comprising: a shielding structure extending in the first direction, and spaced apart from the bit line in the second direction (claim 11)
But YOO teaches,
shielding structures SH may be respectively provided between adjacent ones of the bit lines BL and may be extended parallel to the bit lines BL (see para [0078], FIG. 5C)
Shielding structures SH may reduce a coupling issue between adjacent ones of the bit lines BL, which may occur when an integration density of a semiconductor memory device is increased (para [0079]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify RUU such that a shielding structure SH extending parallel to the substrate in the first direction (X), and spaced apart from the bit line BL in the second direction (Z), according to teaching of YOO, in order to reduce coupling issue between adjacent ones of the bit lines BL, which may occur when an integration density of a semiconductor memory device is increased, as taught by YOO above.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (US 2022/0223732 A1) in view of Yu et al. (US 2022/0115393 A1)
Regarding claim 20, RYU teaches,
PNG
media_image4.png
613
653
media_image4.png
Greyscale
A semiconductor memory device (FIG. 10as annotated above) comprising:
…..a substrate(100, para [0028]);
a bit line (120], para [0030])……., and extending in a first direction(X) ;
a protruding insulating pattern (112, para [0028]) on the substrate, the protruding insulating pattern including a channel trench (130t, Fig. 4, para [0034]) exposing the bit line (as seen in FIG. 4,130t formed on both sides of bit line 120 in direction Y and therefore exposing bit line 120 in direction Y, similar way CH_T exposing BL in direction D1 in FIG. 3 of the disclosure) and
the protruding insulating pattern extending in a second direction (Z) intersecting the first direction (X);
a channel structure (130, para [0041]) in the channel trench, and the channel structure including a horizontal part (horizontal portion of 130 as marked) , and a first vertical part (vertical portion of 130 on left as marked above) and a second vertical part (vertical portion of 130 on right as marked above)protruding from the horizontal part;
a liner film (125, para [0093]) between the bit line and the horizontal part of the channel structure, ……..;
a first word line (150A, para [0045]) on the channel structure, and the first word line extending in the second direction (Z);
a second word line (150B) on the channel structure, the second word line extending in the second direction (Z) , and the second word line spaced apart from the first word line in the first direction (X);
a gate insulating film (140, para [0113]) between the first vertical part of the channel structure and the first word line, and between the second vertical part of the channel structure and the second word line;
a gate separation pattern (114, para [0028]) on the horizontal part of the channel structure, and the gate separation pattern separating the first word line and the second word line (as seen);
and a first capacitor (170A, para [0028]) and a second capacitor (170B, para [0028]) on the channel structure, and the first capacitor and a second capacitor respectively connected to the first vertical part of the channel structure and the second vertical part of the channel structure(via landing pads 160A/160B).
But RYU does not explicitly teaches,
a peri-gate structure on the substrate(100);
the bit line (120) is on the peri-gate structure;
the liner film 125 including a nitride (metal nitride),
But RYU additionally teaches,
PNG
media_image5.png
549
537
media_image5.png
Greyscale
a peri-gate structure (obvious gate structure of peripheral circuit element PT including 220 & 230 which may include transistor for sense amplifiers and/or row drivers and/or column and row decoders, para [0072], FIG. 6) on the substrate(100);
and a bit line (120, para [0030]) is on the peri-gate structure;
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify RYU such that a peripheral circuit element PT including a transistor is formed on the substrate 100 such that a peri-gate structure (obvious gate structures of transistors formed as circuit element PT) on the substrate(100) and the bit line (120) is on the peri-gate structure, according to teaching of RYU, in order to form a transistor for sense amplifiers and/or row drivers and/or column and row decoders to form a memory device including the semiconductor memory device, as taught by RYU above
But RYU still does not explicitly teach ,
the liner film (125) including a nitride;
But RYU additionally teaches,
Contact line 125 between bit line 120 and the channel layer 130 (see para [0092], Fig. 10) and may include metal material ( e.g. Ti, Ta) (see para [0093]).
Meanwhile, Yu teaches,
Channel contact HCP between bit line BL and cannel layer CH (Fig. 9) may include metal materials (e.g., copper or tungsten) and metal nitrides (e.g., TiN, TaN, or WIN) (para [0145]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute Ti (metal) with TiN (metal nitride) as a material for the contact line 125 such that the liner film 125 including a nitride (metal nitride TiN), according to teaching of Yoo, since the court has held that a simple substitution of one known element for another (metal nitride for metal) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). (Please see Smith v. Hayashi, 209 USPQ 754 (Bd. of Pat. Inter. 1980)).
Ordinary artisan would have been motivated to use metal nitride over metal as a contact line to channel in order to prevent unwanted silicide formation with metal during fabrication.
Allowable Subject Matter
Claims 5 & 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 5 & 8, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
further comprising:a protruding insulating pattern on the bit line, wherein the bit line includes a first portion that overlaps the protruding insulating pattern in a third direction, and the liner film is not disposed on the first portion of the bit line (claim 5).
further comprising: a gate separation pattern on the bit line, and separating the first word line and the second word line, wherein the gate separation pattern contacts the bit line(claim 8).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights