DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/20/2025 has been entered.
Notice to Applicant
3. This communication is in response to the communication filed 10/20/2025. New prior art has been discovered that appears to teach the limitations recited in the claims thereby necessitating the rejection below. Claims 1-41 are currently pending.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4.1. Claims 1-13, 17-21, 23, 27-30, 34-35, 37-38, and 40-41 are rejected under 35 U.S.C. 103 as being unpatentable over Lietz et al. (EP 3666164), in view of Rao et al. (US 2010/0310143).
CLAIM 1
Lietz teaches a system for processing and displaying medical imaging data onto an electronic display (Lietz: abstract; ¶¶ [0001] “capturing medical images”; FIG. 1), the system comprising:
a memory, wherein the memory is configured to be communicatively coupled to a medical imaging device, and wherein the memory is configured to (Lietz: abstract; ¶¶ [0029] “scope 100 is communicatively coupled to a modulator in their respective network interface…”, [0036]-[0038] “Non-volatile memory”; FIGS. 1-3):
receive one or more frames of video data from the medical imaging device, wherein each frame of the one or more frames comprises a plurality of data portions (Lietz: abstract; ¶¶ [0029] “Each scope 100 is communicatively coupled…for transmitting on the network to the virtual CCU server”, [0030] “video medical scope devices”, [0038] “remote direct memory access (RDMA) signaling to enhance speed and latency in linking the data to desired GPUs””; FIGS. 1-10); and
store the plurality of data portions of each frame of the received video data in one or more storage mediums of the memory (Lietz: abstract; ¶¶ [0029] “Each scope 100 is communicatively coupled…for transmitting on the network to the virtual CCU server”, [0030] “video medical scope devices”, [0038] “remote direct memory access (RDMA) signaling to enhance speed and latency in linking the data to desired GPUs””; FIGS. 1-10);
a first processor, wherein the first processor is configured to (Lietz: abstract; ¶¶ [0027] “a processor”; FIGS. 1-10):
access the plurality of data portions corresponding to a frame of the one or more frames from the memory (Lietz: abstract; ¶¶ [0028] “GPUs 90 for providing the operator interface and control, as well as image processing functions”; FIGS. 1-10);
process the plurality of data portions (Lietz: abstract; ¶¶ [0028] “GPUs 90 for providing the operator interface and control, as well as image processing functions”; FIGS. 1-10); and
transmit the processed plurality of data portions to an electronic display (Lietz: abstract; ¶¶ [0030] “the virtual CCU 72 is operable to…output the encoded manipulated video data to the respective associated video displays”; FIGS. 1-10); and
a second processor, wherein the second processor is communicatively coupled to the first processor, and wherein the second processor is configured to coordinate one or more operations of the first processor (Lietz: abstract; ¶¶ [0033] “a virtual CCU server 70 includes an allocation manager 75 with server manager software, which may be executed by a separate dedicated server CPU processor”, [0042] “”; FIGS. 1-10).
Lietz does not appear to explicitly teach the following:
using a single instruction multiple data (SIMD) processing architecture such that each data portion of the plurality of data portions is separately processed in parallel using one or more common instructions.
Rao, however, teaches the following:
using a single instruction multiple data (SIMD) processing architecture such that each data portion of the plurality of data portions is separately processed in parallel using one or more common instructions (Rao: abstract; ¶¶ [0028] “processor 12 is a general processor (e.g., Pentium single instruction multiple data processor), digital signal processor, three-dimensional data processor, graphics processing unit (GPU), application specific integrated circuit, field programmable gate array, digital circuit, analog circuit, filter, splitter, selector, combinations thereof, or other now known or later developed device for processing medical image data. The processor 12 is a single device, a plurality of devices, or a network. For more than one device, parallel or sequential division of processing may be used”; FIGS. 1-6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the filter bank for ultrasound image enhancement including SIMD processing architecture, as taught by Rao, with the system for operating medical video scopes, as taught by Lietz, with the motivation of enhancing imaging, increase rapid processing, and/or processing a greater amount of data (Rao: ¶¶ [0001]-[0008]).
CLAIM 2
Lietz teaches the system of claim 1, wherein the system comprises an integrated circuit configured to: receive the one or more frames of video data from the medical imaging device; convert each frame of the one or more frames of video data into a plurality of packets, wherein each packet includes a portion of the frame; and transfer the plurality of packets associated with each frame to the memory (Lietz: abstract; ¶¶ [0037] PCIe bus and network connection between GPU/CPU and medical scopes for transmitting video data. An integrated circuit, e.g., in the network interface, which translates from network packets to PCIe packets is implicit—PCIe converts data into packets (e.g., transaction later packets (TLPs), for efficient, serial communication; FIGS. 1-10; See also MPEP § 2144.01 Implicit Disclosure).
CLAIM 3
Lietz teaches the system of claim 2, wherein the plurality of packets are Peripheral Component Interconnect Express (PCle) packets (Lietz: abstract; ¶¶ [0037] PCIe bus and network connection between GPU/CPU and medical scopes for transmitting video data. An integrated circuit, e.g., in the network interface, which translates from network packets to PCIe packets is implicit—PCIe converts data into packets (e.g., transaction later packets (TLPs), for efficient, serial communication; FIGS. 1-10).
CLAIM 4
Lietz teaches the system of claim 2, wherein transferring the plurality of packets to the memory comprises performing a direct memory access (DMA) transfer (Lietz: abstract; ¶¶ [0038] “connection carrying PCIe, for example, or an optical or high speed Ethernet network carrying remote direct memory access (RDMA) signaling to enhance speed and latency in linking the data to the desired GPUs”; FIGS. 1-10).
CLAIM 5
Lietz teaches the system of claim 4, wherein the DMA transfer is controlled by the integrated circuit (Lietz: abstract; ¶¶ [0038] “CPU/GPU server may contain many such cards, such as 16 or 20 cards. The network interfaces 35 may be integrated with individual processing modules 34. The particular network protocol is not limiting, and may be, for example, a Firewire® connection carrying PCIe, for example, or an optical or high speed Ethernet network carrying remote direct memory access (RDMA) signaling to enhance speed and latency in linking the data to the desired GPU”; FIGS. 1-10).
CLAIM 6
Lietz teaches the system of claim 4, wherein the DMA transfer is controlled by the second processor (Lietz: abstract; ¶¶ [0038] “one or more processing devices, typically mounted on processor cards or modules in the server housing…CPU/GPU server may contain many such cards”; FIGS. 1-10).
CLAIM 7
Lietz teaches the system of claim 2, wherein the integrated circuit is configured to: determine that one or more portions of the one or more frames has been received from the medical imaging device; and transmit a signal to the second processor when a determination has been made that the one or more portions of the one or more frames has been received from the medical imaging device (Lietz: abstract; ¶¶ [0045] Synchronization via signals between data transfer and GPU frame processing is implicit in the video/frame processing function of the system; FIGS. 1-10; See also MPEP § 2144.01 Implicit Disclosure).
CLAIM 8
Lietz teaches the system of claim 7, wherein the second processor is configured to: receive the signal from the integrated circuit indicating that a complete frame of the one or more frames has been received from the medical imaging device; and cause the first processor to initiate processing the plurality of data portions upon receiving the signal from the integrated circuit indicating that a complete frame of the one or more frames has been received from the medical imaging device (Lietz: abstract; ¶¶ [0045] Synchronization via signals between data transfer and GPU frame processing is implicit in the video/frame processing function of the system; FIGS. 1-10; See also MPEP § 2144.01 Implicit Disclosure).
CLAIM 9
Lietz teaches the system of claim 7, wherein the first processor is configured to: receive the signal from the integrated circuit indicating that a complete frame of the one or more frames has been received from the medical imaging device; and initiate processing the plurality of data portions upon receiving the signal from the integrated circuit indicating that a complete frame of the one or more frames has been received from the medical imaging device (Lietz: abstract; ¶¶ [0045] Synchronization via signals between data transfer and GPU frame processing is implicit in the video/frame processing function of the system; FIGS. 1-10; See also MPEP § 2144.01 Implicit Disclosure).
CLAIM 10
Lietz teaches the system of claim 2, wherein the integrated circuit is configured to perform one or more image processing algorithms on the received one or more frames of video data (Lietz: abstract; ¶¶ [0035] “the algorithm to perform a particular image processing technique is strictly controlled”, [0050] “process a video image frame relative to the number of graphics algorithms performed on the frame”; FIGS. 1-10; See also MPEP § 2144.01 Implicit Disclosure).
CLAIM 11
Lietz teaches the system of claim 2, wherein the integrated circuit is configured to receive one or more processed images from the first processor and is configured to perform one or more image processing algorithms on the received one or more processed images (Lietz: abstract; ¶¶ [0035] “the algorithm to perform a particular image processing technique is strictly controlled”, [0050] “process a video image frame relative to the number of graphics algorithms performed on the frame”; FIGS. 1-10).
CLAIM 12
Lietz teaches the system of claim 2, wherein the integrated circuit is configured to receive one or more processed images from the first processor using a direct memory access (DMA) transfer (Lietz: abstract; ¶¶ [0038] “System bus 32 connects the optical interfaces to one or more processing devices, typically mounted on processor cards or modules in the server housing. While one processing module 34 is shown, this is not limiting and a typical CPU/GPU server may contain many such cards, such as 16 or 20 cards. The network interfaces 35 may be integrated with individual processing modules 34. The particular network protocol is not limiting, and may be, for example, a Firewire® connection carrying PCIe, for example, or an optical or high speed Ethernet network carrying remote direct memory access (RDMA) signaling to enhance speed and latency in linking the data to the desired GPUs”; FIGS. 1-10).
CLAIM 13
Lietz teaches the system of claim 11, wherein the integrated circuit comprises one or more output ports and is configured to output the received one or more processed images to the electronic display using the one or more output ports (Lietz: abstract; ¶¶ [0052] “device interface 700 would typically perform multiplexing or open multiple ports to provide a data link for both the display/UI 200 and the scope 100”; FIGS. 1-10).
CLAIM 17
Lietz teaches the system of claim 13, wherein the system comprises a multiplexer, wherein the multiplexer comprises: a first input communicatively coupled to the output port of the integrated circuit; a second input of the multiplexer communicatively coupled to an output port of the first processor; and an output port communicatively coupled to the electronic display; wherein the multiplexer is configured to select the first input or the second input to be transmitted to the electronic display using the output port based on one or more control signals received from the integrated circuit (Lietz: abstract; ¶¶ [0027], [0051, [0052] “device interface 700 would typically perform multiplexing or open multiple ports to provide a data link for both the display/UI 200 and the scope 100. As can be understood, video medical scopes using a device interface module 700 can be used concurrently with the same virtual CCU server as those having an integrated network interface”], [0070]; FIGS. 1-10; See also MPEP § 2144.01 Implicit Disclosure).
CLAIM 18
Lietz teaches the system of claim 2, wherein the integrated circuit is configured to: receive an image from the first processor to be overlaid on the one more received processed images from the first processor; superimpose the received image onto the one or more received processed images to generate a composite image; and transmit the composite image to the electronic display (Lietz: abstract; ¶¶ [0058] “overlaying video streams”; FIGS. 1-10).
CLAIM 19
Lietz teaches the system of claim 2, wherein the integrated circuit is a field programmable gate array (FPGA) (Lietz: abstract; ¶¶ [0027] “the term module refers to an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, or other suitable components that provide the described functionality”, [0034] “programmable hardware such as field-programmable-gate-array (FPGA) devices”; FIGS. 1-10).
CLAIM 20
Lietz teaches the system of claim 2, wherein the integrated circuit is configured to be communicatively coupled to a light source, and wherein the integrated circuit is configured to operate the light source (Lietz: abstract; ¶¶ [0027], [0059] The system includes a “white light” imaging mode (i.e., light source).; FIGS. 1-10).
CLAIM 21
Lietz teaches the system of claim 2, wherein the integrated circuit is configured to determine if the first or second processor has failed and, if it is determined that the first or second processor has failed: perform one or more image processing algorithms on the received one or more frames of video data to generate one or more processed frames of video data; and transmit the one or more processed frames of video data to the electronic display (Lietz: abstract; ¶¶ [0062] Other/additional GPUs may be used to process images/video in the event of hardware failure (e.g., processor(s) has failed) such as CPU OR GPU failure., [0069]; FIGS. 1-10).
CLAIM 23
Lietz teaches the system of claim 1, wherein the system comprises a third processor configured to perform one or more image signal processing algorithms on the received one or more frames of video data (Lietz: abstract; ¶¶ [0070]; FIGS. 1-10).
CLAIM 27
Lietz teaches the system of claim 1, wherein the second processor is configured to execute an operating system configured to manage operation of the first processor (Lietz: abstract; ¶¶ [0032], [0036]; FIGS. 1-10; See also MPEP § 2144.01 Implicit Disclosure).
CLAIM 28
Lietz teaches the system of claim 1, wherein the first processor is a graphics processing unit (GPU) (Lietz: abstract; ¶¶ [0025], [0028]; FIGS. 1-10).
CLAIM 29
Lietz teaches the system of claim 1, wherein the first processor is configured to be communicatively coupled to a light source, and wherein the first processor is configured to operate the light source (Lietz: abstract; ¶¶ [0027], [0059] The system includes a “white light” imaging mode (i.e., light source)., [0070]; FIGS. 1-10).
CLAIM 30
Lietz teaches the system of claim 1, wherein the second processor is configured to be communicatively coupled to a light source, and wherein the second processor is configured to operate the light source (Lietz: abstract; ¶¶ [0027], [0059] The system includes a “white light” imaging mode (i.e., light source)., [0070]; FIGS. 1-10).
CLAIM 34
Lietz teaches the system of claim 1, wherein the memory is a buffer that is part of the first processor (Lietz: abstract; ¶¶ [0037] “RAM”, [0040]-[0042]; FIGS. 1-10).
CLAIM 35
Lietz teaches the system of claim 1, wherein the memory is a system memory shared by the first and second processors (Lietz: abstract; ¶¶ [042], [0075]; FIGS. 1-10).
CLAIM 37
Lietz teaches the system of claim 1, wherein the first processor is configured to perform video encoding on the received one or more frames of video data (Lietz: abstract; ¶¶ [0030] “operable to receive the raw image data from the scope 100, for example in the form of serialized frame data, manipulate visual characteristics of the video data via image or video processing, encode the manipulated video data, and process the control data, to output the encoded manipulated video data to the respective associated video displays over the optical network”, [0047]; FIGS. 1-10).
CLAIM 38
Lietz teaches the system of claim 37, wherein performing video encoding on the received one or more frames comprises applying H.264 encoding on the received one or more frames of video data (Lietz: abstract; ¶¶ [0040] Nvidia GPUs apply video compression standards including H.264 encoding.; FIGS. 1-10).
CLAIM 40
Lietz teaches the system of claim 1, wherein the electronic display and the medical imaging device are operated using a common clock signal generated by the system (Lietz: abstract; ¶¶ [0025] “a virtual CCU server across an optical network, connecting to the scope or camera and to a display/user interface located in the room with the scope or camera”, [0030] “virtual CCU 72 is operable to receive the raw image data from the scope 100, for example in the form of serialized frame data, manipulate visual characteristics of the video data via image or video processing, encode the manipulated video data, and process the control data, to output the encoded manipulated video data to the respective associated video displays over the optical network, and to output the processed control data to the respective video medical scope for controlling an operational aspect of the respective video medical scope”, [0033] CCU includes a CPU that controls the video scope, display, etc. CPUs have a common clock signal. ; FIGS. 1-10).
CLAIM 41
Claim 41 repeats substantially the same limitations as those in claim 1. As such, claim 41 is rejected for substantially the same reasons given for claim 1 and are incorporated herein.
4.2. Claims 14-16, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lietz et al. (EP 3666164), in view of Rao et al. (US 2010/0310143), and further in view of Wang et al. (US 2022/0253980).
CLAIM 14
Lietz and Rao do not appear to explicitly teach the system of claim 13, wherein the one or more output ports comprise high- definition multimedia interface (HDMI) output ports.
Wang, however, teaches wherein the one or more output ports comprise high- definition multimedia interface (HDMI) output ports (Wang: abstract; ¶¶ [0034]-[0037]; FIGS. 1-2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the image system including output ports, as taught by Wang, with the filter bank for ultrasound image enhancement including SIMD processing architecture, as taught by Rao, with the system for operating medical video scopes, as taught by Lietz, with the motivation of facilitating the direct display of processed images (Wang: ¶¶ [0034]-[0037]).
CLAIM 15
Lietz and Rao do not appear to explicitly teach the system of claim 13, wherein the one or more output ports comprise DisplayPorts compatible output ports.
Wang, however, teaches wherein the one or more output ports comprise DisplayPorts compatible output ports (Wang: abstract; ¶¶ [0034]-[0037]; FIGS. 1-2).
The motivation to include the teachings of Wang with the teachings of Lietz and Rao is the same as that of claim 14 above and is incorporated herein.
CLAIM 16
Lietz and Rao do not appear to explicitly teach the system of claim 11, wherein the one or more output ports comprise Serial Digital Interface (SDI) output ports.
Wang, however, teaches wherein the one or more output ports comprise Serial Digital Interface (SDI) output ports (Wang: abstract; ¶¶ [0034]-[0037]; FIGS. 1-2).
The motivation to include the teachings of Wang with the teachings of Lietz and Rao is the same as that of claim 14 above and is incorporated herein.
CLAIM 22
Lietz and Rao do not appear to explicitly teach the system of claim 1, wherein the memory is configured to receive the one or more frames of video data in a mobile industry processor interface (MIPI) camera serial interface (format).
Wang, however, teaches wherein the memory is configured to receive the one or more frames of video data in a mobile industry processor interface (MIPI) camera serial interface (format) (Wang: abstract; ¶¶ [0034]-[0037] “with common image output interfaces like mobile industry processor interface (MIPI)”; FIGS. 1-2).
The motivation to include the teachings of Wang with the teachings of Lietz and Rao is the same as that of claim 14 above and is incorporated herein.
4.3. Claims 24-26, 36, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Lietz et al. (EP 3666164), in view of Rao et al. (US 2010/0310143), and further in view of Tadi et al. (US 2020/0177870).
CLAIM 24
Lietz and Rao do not appear to explicitly teach the system of claim 23, wherein the one or more image signal processing algorithms includes a de-mosaic algorithm.
Tadi, however, teaches wherein the one or more image signal processing algorithms includes a de-mosaic algorithm (Tadi: abstract; ¶¶ [0008] “apparatus further comprises a de-mosaicing module”, [0222] “de-mosaic algorithm”; FIGS. 13A-H).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the image system including a de-mosaic algorithm, as taught by Tadi, with the filter bank for ultrasound image enhancement including SIMD processing architecture, as taught by Rao, with the system for operating medical video scopes, as taught by Lietz, with the motivation of enhancing image quality (Tadi: ¶¶ [0201]).
CLAIM 25
Lietz and Rao do not appear to explicitly teach the system of claim 23, wherein the one or more image signal processing algorithms includes a noise reduction algorithm.
Tadi, however, teaches wherein the one or more image signal processing algorithms includes a noise reduction algorithm (Tadi: abstract; ¶¶ [0155] “remove or at least reduce noise as necessary, and can also be used to normalize the signals”, [0175]-[0177], [0313] “algorithm for noise reduction”).
The motivation to include the teachings of Tadi with the teachings of Lietz and Rao is the same as that of claim 24 above and is incorporated herein.
CLAIM 26
Lietz and Rao do not appear to explicitly teach the system of claim 1, wherein processing the plurality of data portions comprises applying one or more image signal processing algorithms selected from the group consisting of: Pixel defect correction, color leakage correction, de-mosaic, spatial and temporal noise reduction filters, sharpening filters, color space conversion, image stabilization, overlay of multiple image sensors, image augmentation, gamma correction, dewarping, and distortion correction.
Tadi, however, teaches wherein processing the plurality of data portions comprises applying one or more image signal processing algorithms selected from the group consisting of: Pixel defect correction, color leakage correction, de-mosaic, spatial and temporal noise reduction filters, sharpening filters, color space conversion, image stabilization, overlay of multiple image sensors, image augmentation, gamma correction, dewarping, and distortion correction (Tadi: abstract; ¶¶ [0008] “apparatus further comprises a de-mosaicing module”, [0186] “color correction”, [0222] “de-mosaic algorithm”, [0318] “pixel correction”; FIGS. 13A-H).
The motivation to include the teachings of Tadi with the teachings of Lietz and Rao is the same as that of claim 24 above and is incorporated herein.
CLAIM 36
Lietz and Rao do not appear to explicitly teach the system of claim 1, wherein the first processor is configured to perform one or more iterative algorithms on the plurality of data portions, wherein performing an iterative algorithm comprises: applying a first common instruction to each data portion of the plurality of data portions to generate a plurality of first processed data portions; storing each data portion of the plurality of first processed data portions in the memory; and applying a second common instruction to each data portion of the plurality of first processed data portions stored in the memory to generate a plurality of second processed data portions.
Tadi, however, teaches wherein the first processor is configured to perform one or more iterative algorithms on the plurality of data portions, wherein performing an iterative algorithm comprises: applying a first common instruction to each data portion of the plurality of data portions to generate a plurality of first processed data portions; storing each data portion of the plurality of first processed data portions in the memory; and applying a second common instruction to each data portion of the plurality of first processed data portions stored in the memory to generate a plurality of second processed data portions (Tadi: abstract; ¶¶ [0164]-[0177] The system/method apply pre-processing (i.e., first common instruction) and subsequently apply other processing such as colorization, etc. (i.e., second common instruction)., [0402] “iterative solution”; FIGS. 1-4B).
The motivation to include the teachings of Tadi with the teachings of Lietz and Rao is the same as that of claim 24 above and is incorporated herein.
CLAIM 39
Lietz and Rao do not appear to explicitly teach the system of claim 1, wherein the first processor is configured to perform one or more image processing algorithms on the received one or more frames of video data selected from the group consisting of pixel defect correction, color leakage correction, demosaicing, spatial filtering, temporal noise filtering, sharpening filtering, color space conversion, image stabilization, image augmentation, gamma correction, dewarping, image compression, image decompression, and distortion correction.
Tadi, however, teaches wherein the first processor is configured to perform one or more image processing algorithms on the received one or more frames of video data selected from the group consisting of pixel defect correction, color leakage correction, demosaicing, spatial filtering, temporal noise filtering, sharpening filtering, color space conversion, image stabilization, image augmentation, gamma correction, dewarping, image compression, image decompression, and distortion correction (Tadi: abstract; ¶¶ [0008] “apparatus further comprises a de-mosaicing module”, [0186] “color correction”, [0222] “de-mosaic algorithm”, [0318] “pixel correction”; FIGS. 13A-H).
The motivation to include the teachings of Tadi with the teachings of Lietz and Rao is the same as that of claim 24 above and is incorporated herein.
4.4. Claims 31-33 are rejected under 35 U.S.C. 103 as being unpatentable over Lietz et al. (EP 3666164), in view of Rao et al. (US 2010/0310143), and further in view of Haemel et al. (US 2020/0303060).
CLAIM 31
Lietz and Rao do not appear to explicitly teach the system of claim 1, wherein processing the plurality of data portions comprises applying one or more artificial intelligence applications to the plurality of data portions.
Haemel, however, teaches wherein processing the plurality of data portions comprises applying one or more artificial intelligence applications to the plurality of data portions (Haemel: abstract; ¶¶ [0094] “train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services”, [0095]-[0096] “processing to be performed on input image data using one or more networks”, [0372]-[0374], [0390]; FIGS. 1-5).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the image analysis system using artificial intelligence, as taught by Haemel, with the filter bank for ultrasound image enhancement including SIMD processing architecture, as taught by Rao, with the system for operating medical video scopes, as taught by Lietz, with the motivation of facilitating image data processing (Haemel: ¶¶ [0002]-[0003], [0372]-[0374]).
CLAIM 32
Lietz and Rao do not appear to explicitly teach the system of claim 31, wherein the first processor comprises one or more tensor cores configured to perform matrix operations.
Haemel, however, teaches wherein the first processor comprises one or more tensor cores configured to perform matrix operations (Haemel: abstract; ¶¶ [0340]-[0341] “Tensor cores are configured to perform matrix operations”; FIGS. 1-5).
The motivation to include the teachings of Haemel with the teachings of Lietz and Rao is the same as that of claim 31 above and is incorporated herein.
CLAIM 33
Lietz and Rao do not appear to explicitly teach the system of claim 32, wherein the one or more tensor cores are configured to apply the one or more artificial intelligence applications to the plurality of data portions.
Haemel, however, teaches wherein the one or more tensor cores are configured to apply the one or more artificial intelligence applications to the plurality of data portions (Haemel: abstract; ¶¶ [0340]-[0341]; FIGS. 1-5).
The motivation to include the teachings of Haemel with the teachings of Lietz and Rao is the same as that of claim 31 above and is incorporated herein.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael Tomaszewski whose telephone number is (313)446-4863. The examiner can normally be reached M-F 5:30 am - 2:30 pm.
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/MICHAEL TOMASZEWSKI/Primary Examiner, Art Unit 3681