DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the application filed December 27, 2023.
Claim Objections
Claims 1 , 5-6, 8, 10, 12, 14 and 17 are objected to because of the following informalities:
In regard to claims 1, 8, 10, 12, 14 and 17, “wherein:” should have been wherein in line 9 of claim 1, line 5 of claim 8, line 1 of claim 10, line 1 of claim 12, line 1 of claim 14 and line 3, page 3 of claim 17; and
In regard to claims 5-6, “placeholder epitaxial” should have been epitaxial placeholder in line 1 of both claims.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claims 1 and 11, it is not understood how the semiconductor structure extends laterally with the first interconnect and the second interconnect when the first and second interconnect are within the semiconductor structure. The claim reads as though the semiconductor structure is a separate entity from the first and second interconnects.
In regard to claim 1 concerning the first and second lateral ends, lateral side-to-side, horizontal. Therefore, does the Applicant mean the left-side angled vertical end and the right-side angled vertical end of the first lead?
Claims 2-10 are rejected as being dependent upon rejected claim 1.
Claims 12-20 are rejected as being dependent upon rejected claim 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
As best understood, claim(s) 1-2, 4-5, 8-16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (CN 116938220 A1).
In regard to claim 1, Huang et al. teach a semiconductor structure 100 that extends laterally with a first interconnect BM0 on one side and a second interconnect M0 on an opposing side separated from the first interconnect BM0 by a longitudinal thickness of an insulating member RX that extends laterally along the first interconnect BM0 and the second interconnect M0, the semiconductor structure 100 comprising: a first source/drain (S/D) (S/D at Via-v1) positioned in the insulating member RX between the first interconnect BM0 and the second interconnect M0; a second S/D (S/D at VB-v2) positioned in the insulating member RX adjacent to the first S/D (S/D at Via-v1); and a first lead Via-v1 electrically connected to the first S/D (S/D at Via-v1) and to the second interconnect M0 and electrically insulated from the second S/D (S/D at VB-v2), wherein: a first lateral end of the first lead Via-v1 is angled inwards towards the first S/D (S/D at Via-v1) at a first acute angle relative to a lateral direction; and a second lateral end of the first lead Via-v1 is angled away from the first S/D (S/D at Via-v1) at a second acute angle relative to the lateral direction (Figure 9, pages 16-20).
In regard to claim 2, Huang et al. teach the first acute angle being different (in location) from the second acute angle (Figure 9, pages 16-20).
In regard to claim 4, Huang et al. teach the second S/D (S/D at VB-v2) electrically connected to the first interconnect BM0 (Figure 9, pages 16-20).
In regard to claim 5, Huang et al. teach a placeholder epitaxial MD in direct contact with the second S/D (S/D at VB-v2) on a side of the second S/D (S/D at VB-v2) that is closest to the first lead (S/D at Via-v1) (Figure 9, pages 16-20).
In regard to claim 8, Huang et al. teach a third S/D (S/D far right) positioned in the insulating member RX adjacent to the second S/D (S/D at VB-v2) on an opposite side from the first S/D (S/D at Via-v1); and a second lead VB-v1 electrically connected to the third S/D (S/D far right) and to the second interconnect M0 and electrically insulated from the second S/D (S/D at VB-v2) and the first lead BM0, wherein: a third lateral end of the second lead M0 is angled inwards towards the third S/D (S/D far right) at a third acute angle relative to the lateral direction; and a fourth lateral end of the second lead M0 is angled away from the third S/D (S/D far right) at a fourth acute angle relative to the lateral direction (Figure 9, pages 16-20).
In regard to claim 9, Huang et al. teach the first acute angle and the second acute angle are oriented opposite (opposite ends) to the third acute angle and the fourth acute angle (Figure 9, pages 16-20).
In regard to claim 10, Huang et al. teach the insulating member RX comprising a plurality of insulators (insulating sections between S/Ds); and an insulator of the plurality of insulators (insulating sections between S/Ds) positioned between the first lead Via-v1 and the second lead VB-v2 to electrically insulate the first lead Via-v1 from the second lead VB-v2 (Figure 9, pages 16-20).
In regard to claim 11, Huang et al. teach a semiconductor structure 100 that extends laterally with a first interconnect BM0 on one side and a second interconnect M0 on an opposing side separated from the first interconnect BM0 by a longitudinal thickness of an insulating member RX that extends laterally along the first interconnect BM0 and the second interconnect M0, the semiconductor structure 100 comprising: a first source/drain (S/D) (S/D at Via-v1) positioned in the insulating member RX between the first interconnect BM0 and the second interconnect M0, wherein the insulating member RX comprises a plurality of insulators; a second S/D (S/D at VB-v2) positioned in the insulating member RX adjacent to the first S/D (S/D at Via-v1); a third S/D (S/D far right) positioned in the insulating member RX adjacent to the second S/D (S/D at VB-v2) on the opposite side from the first S/D (S/D at Via-v1); a first lead Via-V1 electrically connected to the first S/D (S/D at Via-v1) and to the second interconnect M0 and electrically insulated from the second S/D (S/D at VB-v2); a second lead VB-v2 electrically connected to the first S/D (S/D at Via-v1) and to the second interconnect M0 and electrically insulated from the second S/D (S/D at VB-v2); and an insulator of the plurality of insulators (insulating sections between S/Ds) positioned between the first lead (S/D at Via-v1) and the second lead VB-v2 to electrically insulate the first lead Via-v1 from the second lead VB-v2 (Figure 9, pages 16-20).
In regard to claim 12, Huang et al. teach a first lateral end of the first lead Via-v1 angled inwards towards the first S/D (S/D at Via-v1) at a first acute angle relative to a lateral direction; and a second lateral end of the first lead Via-v1 in contact with the insulator (insulating sections of RX) and is angled towards the third S/D (S/D far right) at a second acute angle relative to the lateral direction (Figure 9, pages 16-20).
In regard to claim 13, Huang et al. teach the first acute angle being different (in location) from the second acute angle (Figure 9, pages 16-20).
In regard to claim 14, Huang et al. teach a third lateral end of the second lead VB-v2 angled inwards towards the third S/D (S/D far right) at a third acute angle; and a fourth lateral end of the second lead VB-v2 in contact with the insulator (insulating sections of RX) and is angled towards the second S/D (S/D at VB-v2) at a fourth acute angle (Figure 9, pages 16-20).
In regard to claim 15, Huang et al. teach the first acute angle and the fourth acute angle having approximately a same value and an opposite orientation (Figure 9, pages 16-20).
In regard to claim 16, Huang et al. teach the second acute angle and the third acute angle have approximately a same value and an opposite orientation (Figure 9, pages 16-20).
In regard to claim 19, Huang et al. teach the second S/D (S/D at VB-v2) electrically connected to the first interconnect BM0 (Figure 9, pages 16-20).
In regard to claim 20, Huang et al. teach no portion of the second lead lVB-v2 aps the second S/D (S/D at VB-v2) laterally (Figure 9, pages 16-20).
Allowable Subject Matter
As best understood, claims 3, 6-7 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The following patents are cited to further show the state of the art with respect to semiconductor structures:
Abu-Rahma et al. (US 2023/0298996 A1) Chang et al. (US 2023/0068359 A1)
Kim et al. (US 2023/0317596 A1) Peng et al. (US 2021/0391318 A1)
Wei (US 2022/0310514 A1) Xie et al. (US 2023/0215767 A1)
You et al. (US 2024/0169137 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
IMS
February 23, 2026
/IDA M SOWARD/Primary Examiner, Art Unit 2898